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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.3
RGMII AC Timing Specification
Figure 37
and
Figure 37. RGMII Interface Timing
Table 48. RGMII Interface Timing Parameters
Symbol
TskewT
TskewR
Tcyc
Duty_T
Duty_G
Tr/Tf
1. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater
than 1.5 ns is added to the associated clock signal.
2. For 10 Mbps and 100 Mbps Tcyc scales to 400 ns +/– 40 ns and 40 ns +/– 4 ns respectively.
3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's
clock domain, as long as minimum duty cycle is not violated and stretching occurs for no more than three
Tcyc of the lowest speed transitioned between.
141
Table 48
provide RGMII interface timing parameters.
TXC
(at Transmitter)
TD[3:0]
TD[3:0]
TX_CTL[n]
TXEN
TXC
(at Receiver)
RXC
(at Transmitter)
RD[3:0]
RD[3:0]
RX_CTL
RXDV
RXC
(at Receiver)
Parameter
Data-to-Clock Output Skew (at Transmitter)
Data-to-Clock Input Skew (at Receiver)
2
Clock Cycle Duration
2
Duty Cycle for Gigabit
3
Duty Cycle for 10/100T
Rise/Fall Time (20–80%)
TSkewT
TD[7:4]
TSkewR
TXERR
TSkewT
RD[7:4]
TSkewR
RXERR
Min
Typ
-500
1
1
7.2
45
40
–
B3251-01
Max
Unit
0
500
ps
–
2.8
ns
8
8.8
ns
50
55
%
50
60
%
–
.75
ns
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
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