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Intel 41210 Design Manual

Serial to parallel pci bridge
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Intel® 41210 Serial to Parallel PCI
Bridge
Design Guide
May 2005
Order Number:
278801-004

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Summary of Contents for Intel 41210

  • Page 1 Intel® 41210 Serial to Parallel PCI Bridge Design Guide May 2005 Order Number: 278801-004...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

  • Page 3: Table Of Contents

    PCI General Layout Guidelines ...33 8.3.1 PCI Pullup Resistors Not Required...34 PCI Clock Layout Guidelines ...35 PCI-X Topology Layout Guidelines...38 ® Intel 41210 Serial to Parallel PCI Bridge Design Guide Layout Analysis ...38 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Contents...
  • Page 4 10.1.2 PCI Express Analog Voltage Filter ... 50 10.1.3 Bandgap Analog Voltage Filter ... 51 10.2 Intel® 41210 Serial to Parallel PCI Bridge Reference and Compensation Pins ... 53 10.2.1 SM Bus ... 54 41210 Bridge Customer Reference Boards... 55 11.1...
  • Page 5 13 PCI 66 MHz Embedded Table ...42 14 PCI 33 MHz Embedded Routing Recommendations...43 15 Adapter Card Routing Recommendations ...46 16 Recommended R, L and C Values for 41210 Bridge Analog Filter Circuits ...49 17 SMBUs Address Configuration ...54 18 CRB Board Stackup...56 19 PCI Express Interface Signals ...59...
  • Page 6 Contents This page intentionally left blank Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 7: About This Document

    Terminology and Definitions Table 1 provides a list of terms and definitions that may be useful when working with the 41210 Bridge product. Table 1. Terminology and Definitions (Sheet 1 of 2)
  • Page 8 • Etching removes unwanted copper • Board is tinned, coated with solder mask Example of a Four-Layer Stack and silk screened Victim Network Aggressor Network ® core DDR SDRAM or Peripheral Bus Interface Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 9: Introduction

    ® The Intel 41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification, Revision 1.0. The two PCI bus interfaces are fully compliant to the PCI Local Bus Specification, Revision 2.3.

  • Page 10: Power Management

    — Code space: estimated code size is ~2K words of program space and 32 words of RAM Figure 1shows this SMBus and the data transfer that occurs between C and SMBus Protocols Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 11: Microcontroller Connections To The 41210 Bridge

    Figure 1. 41210 Bridge Microcontroller Block Diagram Microcontroller 2.4.2 Microcontroller Connections to the 41210 Bridge The following diagram shows the SMB interface from the 41210 Bridge to the microcontroller. Figure 2. 41210 Bridge Microcontroller Connections Intel fi 41210 Bridge SMBDAT...

  • Page 12: Jtag

    • Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a Related Documents • Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS), Revision 1.0. • PCI Express Specification, Revision 1.0, from www.pci-sig.com. • PCI Express Design Guide, Revision 0.5 •...

  • Page 13: Intel ® 41210 Serial To Parallel Pci Bridge Applications

    41210 Serial to Parallel PCI Bridge Applications This section provides a block diagram for a typical the 41210 Bridge application. This application shows a PCI-E adapter card with two Dual 2Gb Fibre Channel controllers. Each of the PCI-X bus segments is connected to the Dual 2Gb Fibre Channel chip running at 133MHz. The two Dual FC chips provides the four 2Gb/s outputs.
  • Page 14 Introduction This page intentionally left blank Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 15: Package Information

    Package Information Package Specification The 41210 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch. Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Handling Exclusion Area 0.550 in. Intel® 41210 Serial to Parallel PCI Bridge Design Guide 0.550 in.

  • Page 16: Bottom View - 41210 Bridge 567-Ball Fcbga Package Dimensions

    Package Information Figure 6. Bottom View - 41210 Bridge 567-Ball FCBGA Package Dimensions 4X 0.635 4X 15.500 23X 1.270 23X 1.270 8X 14.605 (0.895) 29.2100 31.00 – 0.100 0.200 - B - Intel® 41210 Serial to Parallel PCI Bridge Design Guide 31.00 –...

  • Page 17: Side View - 41210 Bridge 567-Ball Fcbga Package Dimensions

    Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions FC BGA Substrate 1.940 – 0.150 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Package Information Detail J Scale 5:1 Underfill Epoxy Detail H Scale 5:1 1.170 – 0.085 0.600 –...
  • Page 18 Package Information This page intentionally left blank. Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 19: Power Plane Layout

    Power Plane Layout This chapter provides details on the decoupling and voltage planes needed to bias the 41210 Bridge package. 41210 Bridge Decoupling Guidelines Table 2 lists the decoupling guidelines for the 41210 Bridge. decoupling capacitors around the 41210 Bridge ball grid pins.

  • Page 20: Decoupling Placement For Pci/Pci-X 1.5V And 3.3V Voltage Planes

    Power Plane Layout Figure 9. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes Capacitor Legend 0603-0.1 F 0603-1 F 1206-10 F Intel® 41210 Serial to Parallel PCI Bridge Design Guide B2714-01...

  • Page 21: Split Voltage Planes

    PCI Express Voltage PCI Express Voltage Split Voltage Planes There are two 1.5V voltage planes that supply power to the 41210 Bridge: • VCC15:1.5V ±5% (1.5V core voltage) • VCCPE:1.5V ±3% (1.5V PCI Express voltage) The 41210 Bridge core (VCC15), PCI-Express (VCCPE) voltages should be supplied by two separate voltage regulators or a single regulator.

  • Page 22: 41210 Bridge Single-Layer Split Voltage Plane

    Power Plane Layout Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies. Figure 10. 41210 Bridge Single-Layer Split Voltage Plane Core Express B2715-01 Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 23: 41210 Bridge Reset And Power Timing Considerations

    The following steps are the power sequencing requirements that must be followed with the 41210 Bridge: 1. The 41210 Bridge requires that the VCC33 voltage rail be no less than 0.5V below VCC15 (absolute voltage value) at all times during 41210 operation, including during system power up and power down.
  • Page 24 41210 Bridge Reset and Power Timing Considerations This page intentionally left blank. Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 25: General Routing Guidelines

    PCI Express bus and PCI-X bus interfaces General Routing Guidelines This section details general routing guidelines for designing with the 41210 Bridge. The order in which signals are routed varies from designer to designer. Some designers prefer to route all clock signals first, while others prefer to route all high-speed bus signals first.

  • Page 26: Emi Considerations

    The below link can provide some useful general EMI guidelines considerations: http://developer.intel.com/design/auto/mcs96/applnots/272673.htm victim Reference Plane Figure Connector Connector Pins GND PCB Layer Intel® 41210 Serial to Parallel PCI Bridge Design Guide Reduce Crosstalk: - Maximize P - Minimize H A9259-01 B. Correct method A9260-01...

  • Page 27: Power Distribution And Decoupling

    Decoupling Inadequate high-frequency decoupling results in intermittent and unreliable behavior. A general guideline recommends that you use the largest easily available capacitor in the lowest inductance package. For specific decoupling requirements for a 41210 Bridge application please refer to Chapter...

  • Page 28: Differential Impedance

    “Terminating Differential Signals on PCBs”, Steve Kaufer and Kelee Crisafulli, Printed Circuit Design, March 1999 differential impedance. This section provides some basic Ground reference plane Z11 Z12 Z21 Z22 Intel® 41210 Serial to Parallel PCI Bridge Design Guide B2716 -01 B2717 -01...

  • Page 29: Board Layout Guidelines

    Board Layout Guidelines This chapter provides details on adapter card stackup suggestions. It is highly recommended that signal integrity simulations be run to verify each 41210 Bridge PCB layout especially if it deviates from the recommendations listed in these design guidelines.

  • Page 30: Adapter Card Stackup

    L2 (GND) L4 (VCC) L5 (VCC) L7 (GND) Stripline Stripline Trace Trace Width Spacing Intel® 41210 Serial to Parallel PCI Bridge Design Guide Trace Height 1 Trace Height 2 Stripline Trace Thickness Trace Height 3 Core Thickness Plane Thickness B1436-01...

  • Page 31: Pci-X Layout Guidelines

    A_INTC A_INTD The 41210 Bridge will use its primary bus number and device number in the Requester ID field for the PCI Express INTx messages. As stated in the PCI Express specification, the function number is reserved for interrupt messages and will always be 0.

  • Page 32: Interrupt Routing For Devices Behind A Bridge

    Within a group, priority is round-robin. The entire low-priority group represents one slot in the high priority group. The 41210 Bridge provides a 16-bit arbiter control register to control two aspects of the internal arbiter behavior:...

  • Page 33: Pci Resistor Compensation

    A_INTD#, B_INTA#, B_INTB#, B_INTC#, B_INTD# and TCK, TDI, TDO, TMS and TRST#. Most PCI-X signals are timing critical. These signals have length restrictions for propagation, setup, and hold requirements. Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines RCOMP –...

  • Page 34: Pci Pullup Resistors Not Required

    8.3.1 PCI Pullup Resistors Not Required PCI control signals on the 41210 Bridge do NOT require pullup resistors on the adapter card to ensure that they contain stable values when no agent is actively driving the bus. These include: A_ACK64#, A_AD[63:32], A_CBE#[7:4], A_DEVSEL#, A_FRAME#, A_INTA#, A_INTB#,...

  • Page 35: Pci Clock Layout Guidelines

    0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz. A typical PCI-X application may require separate clock point-to-point connections distributed to each PCI device. The 41210 Bridge provides seven buffered clocks on the PCI bus to connect to multiple PCI-X devices. The length matching requirements.

  • Page 36: Pci Clock Distribution And Matching Requirements

    – Minimum separation between two segments of the same CLK line, "a". ® Intel A_CLKO0 41210 A_CLKO1 Bridge A_CLKO2 A_CLKO3 A_CLKO4 A_CLKO6 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Device 1 Device 2 Device 3 Device 4 Device 5 B1499-04...

  • Page 37: Pci-X Clock Layout Requirements Summary

    (on serpentine layout), “a” dimension Stripline Trace Spacing: Separation between clocks and other lines Length Matching Requirements Total Length of the 41210 Bridge PCI CLKs on the adapter card A_CLKIN, B_CLKIN Series Termination A_CLK[6:0], B_CLK[6:0] Series Termination Routing Guideline 1 Routing Guideline 2 Intel®...

  • Page 38: Pci-X Topology Layout Guidelines

    Receiver Model: generic models for PCI-X and PCI • Driver Package Model: Preliminary 41210 Bridge Model • Cross talk and ISI impact on timing were not modeled Maximum Loads +/- 15% single-ended impedance Intel® 41210 Serial to Parallel PCI Bridge Design Guide Maximum Number of Slots...

  • Page 39: Embedded Pci-X 133 Mhz

    TL_EM1 and TL_EM2 to the embedded device Length Matching Requirements: Number of vias Intel® 41210 Serial to Parallel PCI Bridge Design Guide Table 10 describes the routing recommendations. Routing Guideline for Lower AD Bus Route over an unbroken ground plane...

  • Page 40: Embedded Pci-X 100 Mhz

    1.5” min - 3.5” max Clocks coming form the clock driver must be on the same layer and length matched to within 25 mils. 4 vias max per path Intel® 41210 Serial to Parallel PCI Bridge Design Guide Figure 19 shows B2720 -01...

  • Page 41: Pci-X 66 Mhz Embedded Topology

    Length Matching Requirements: Number of vias Intel® 41210 Serial to Parallel PCI Bridge Design Guide provide routing details for a topology with an embedded PCI-X 66 MHz Routing Guideline for Lower AD Bus Route over an unbroken ground plane...

  • Page 42: Pci 66 Mhz Embedded Topology

    Board Impedance Microstrip Trace Spacing Stripline Trace Spacing Group Spacing Breakout Trace Length 1 TL1: From 41210 Bridge signal Ball to first junction Trace Length TL2 between junctions Trace Length TL_EM1 to TL_EM4 from junction to embedded devices Length Matching Requirements...

  • Page 43: Pci 33 Mhz Embedded Mode Topology

    TL_EM10 from junction to embedded devices Length Matching Requirements Intel® 41210 Serial to Parallel PCI Bridge Design Guide provide routing details for a topology with an embedded PCI 33 MHz Routing Guideline for Lower AD Bus Route over an unbroken ground plane...
  • Page 44 PCI-X Layout Guidelines This page intentionally left blank. Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 45: Pci Express Layout

    PCI Express Layout This section provides an overview of the PCI-Express stackup recommended based on Intel presimulation results. For additional information, refer to the Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual or the PCI Express Specification, Revision 1.0a from the www.pcisig.com...

  • Page 46: Pci-Express Layout Guidelines

    Target Differential Impedance: 100 • Driver Model: 41210 Bridge PCI-E IBIS • Receiver Model: 41210 Bridge PCI-E IBIS. Specification model did not meet specifications • Driver Package Model: Preliminary 41210 Bridge model. • No receiver package model used since specification eye is at package pin.
  • Page 47 Length Matching Requirements: Number of vias Intel® 41210 Serial to Parallel PCI Bridge Design Guide 1.0” min - 6.0” max Total allowable intra-pair length mis-match must not exceed 25 mils. Each routing segment should be matched as close as possible. Total skew across all lanes must be less than 20 ns.
  • Page 48 PCI Express Layout This page intentionally left blank. Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 49: Circuit Implementations

    PCI interface, one for the PCI Express interface, and one for the bandgap voltage. The 41210 Bridge lists the recommended filter values for these filter circuits -- any one of the filter circuits can use any one of the four R, L and C combinations shown in Express analog voltage filter.

  • Page 50: Pci Analog Voltage Filters

    Figure 23. PCI Analog Voltage Filter Circuit Note: Three of these PCI filter circuits must be placed on the system board, one for each of the VCCAPCI[2:0] pins on the Intel® 41210 Serial to Parallel PCI Bridge. • Place C as close as possible to package pin.

  • Page 51: Bandgap Analog Voltage Filter

    • Min trace space to other nets = 30 mils. 10.1.3 Bandgap Analog Voltage Filter Figure 25 Shows the Bandgap Analog Voltage Filter. Intel® 41210 Serial to Parallel PCI Bridge Design Guide Board Trace: Board Route Breakout Traces Traces Circuit Implementations Breakout Trace: Trace Width >...

  • Page 52: Bandgap Analog Voltage Filter Circuit

    Trace Length < 600 mils Board Route Breakout 2.5 V Traces Traces Intel® 41210 Serial to Parallel PCI Bridge Design Guide Breakout Trace: Trace Width > 6 mils Trace Spacing < 6 mils Trace Length < 600 mils VCCBGPE Intel 41210 fi...

  • Page 53: Intel® 41210 Serial To Parallel Pci Bridge Reference And Compensation Pins

    PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI Express interface on the Intel® 41210 Serial to Parallel PCI Bridge. The nominal compensation voltage is 0.5V. An external 24.9 ±1% pullup resistor should be used to connect to VCC15. A single pullup resistor can be used to for both of these signals.

  • Page 54: Sm Bus

    Table 17. SMBUs Address Configuration Refer to Section 2.4 microcontroller. Value SMBUS[5] SMBUS[3] SMBUS[2] SMBUS[1] for details on how to use the SMBus to initialize 41210 Bridge registers with a Intel® 41210 Serial to Parallel PCI Bridge Design Guide Table...

  • Page 55: 41210 Bridge Customer Reference Boards

    41210 Bridge Customer Reference Boards This chapter describes the 41210 Bridge Customer Reference Board (CRB). 11.1 Board Stack-up The proposed layout of the PCB is eight layers with the following stackup: • Signal #1 (Top/Component Side) • Ground Plane: GND •...

  • Page 56: Material

    Table 18. CRB Board Stackup Thickness 11.2 Material The following materials are used with the 41210 Bridge CRB: • FR-4, 0.062 in. +/- .007, 1.0 oz Copper Power/GND. • Full length PCI Raw Card (3.3V Universal) 6.2” high x 7.00” long max with ½ inch cut away.

  • Page 57: Board Outline

    11.4 Board Outline Figure 27 provides the mechanical outline of the 41210 Bridge CRB. Figure 27. Mechanical Outline of the 41210 Bridge Intel® 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Customer Reference Boards Intel fi 41210 Bridge...
  • Page 58 41210 Bridge Customer Reference Boards This page intentionally left blank Intel® 41210 Serial to Parallel PCI Bridge Design Guide...

  • Page 59: Design Guide Checklist

    This checklist highlights design considerations that should be reviewed prior to manufacturing an adapter card that implements the 41210 Bridge product. The items contained within this checklist attempt to address important connections to these devices and any critical supporting circuitry. This is not a complete list and does not guarantee that a design will function properly.

  • Page 60: Pci/Pci-X Interface Signals

    X_AD[31:0] and X_CBE#[3:0] signals do not require pullups according to the PCI Specification. Sampled on the rising edge of PERST#. The 41210 Bridge has internal pullup resistors on these signals. Intel® 41210 Serial to Parallel PCI Bridge Design Guide Reason/Impact...
  • Page 61 B_PCIXCAP IDSEL The series resistor on IDSEL should be 200 ±5%. Intel® 41210 Serial to Parallel PCI Bridge Design Guide Recommendations to operate at 66 MHz and not already pulled up by system board. This signal is grounded for 33 MHz operation.

  • Page 62: Miscellaneous Signals

    Recommendations pullup resistor for normal operation. unless otherwise stated. • To retry configuration accesses to the 41210, pull high to 3.3V through a 2K resistor. • To allow configuration accesses to the 41210, ground this pin through a 2K resistor.

  • Page 63: Power And Ground Signals

    Anode will be connected to VCC15 and cathode will be connected to VCC33. Connect to 1.5V power supply. VCCAPE VCCAPCI[2:0] Voltage output of the bandgap filter circuit into 41210 VCCBGPE Bridge, separated from the rest of the VCC15s. See Figure 25 Connect to 1.5V power supply.

  • Page 64: Jtag Signals

    TRST# Connect to ground via a 1K pulldown resistor. Recommendations Internal pull-up Internal pull-up Internal pull-up Internal pull-up should be tied to ground. Intel® 41210 Serial to Parallel PCI Bridge Design Guide Reason/Impact If TAP interface is not used this...

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