Host Controller Initialization; Default Values Of Operational Register Space - Intel IXP45X Developer's Manual

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9.14.1

Host Controller Initialization

After initial power-on or HCReset (hardware or via HCReset bit in the USBCMD
register), all of the operational registers will be at their default values, as illustrated in
Table 167, "Default Values of Operational Register Space" on page
hardware reset, only the operational registers not contained in the Auxiliary power well
will be at their default values.
Table 167.

Default Values of Operational Register Space

Operational Register
USBCMD
USBSTS
USBINTR
FRINDEX
CTRLDSSEGMENT
PERIODICLISTBASE
ASYNCLISTADDR
CONFIGFLAG
PORTSC
In order to initialize the host controller, software should perform the following steps:
• Program the CTRLDSSEGMENT register with 4-Gigabyte segment where all of the
interface data structures are allocated.
• Write the appropriate value to the USBINTR register to enable the appropriate
interrupts.
• Write the base address of the Periodic Frame List to the PERIODICLIST BASE
register. If there are no work items in the periodic schedule, all elements of the
Periodic Frame List should have their T-Bits set to a one.
• Write the USBCMD register to set the desired interrupt threshold, frame list size (if
applicable) and turn the host controller ON via setting the Run/Stop bit.
• Write a 1 to CONFIGFLAG register to route all ports to the EHCI controller (see
Section 9.14.2, "Port Routing and Control" on page
At this point, the host controller is up and running and the port registers will begin
reporting device connects, etc. System software can enumerate a port through the
reset process (where the port is in the enabled state). At this point, the port is active
with SOFs occurring down the enabled port enabled High-speed ports, but the
schedules have not yet been enabled. The EHCI Host controller will not transmit SOFs
to enabled Full- or Low-speed ports. In order to communicate with devices via the
asynchronous schedule, system software must write the ASYNDLISTADDR register with
the address of a control or bulk queue head. Software must then enable the
asynchronous schedule by writing a one to the Asynchronous Schedule Enable bit in the
USBCMD register. In order to communicate with devices via the periodic schedule,
system software must enable the periodic schedule by writing a one to the Periodic
Schedule Enable bit in the USBCMD register. Note that the schedules can be turned on
before the first port is reset (and enabled).
Any time the USBCMD register is written, system software must ensure the appropriate
bits are preserved, depending on the intended operation.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
0x00080000 (0x00080B00 if Asynchronous Schedule Park Capability is a one)
0x00001000
0x00000000
0x00000000
0x00000000
Undefined
Undefined
0x00000000
0x00002000 (w/PPC set to one); 0x00003000 (w/PPC set to a zero)
Default Value (after Reset)
411).
Order Number: 306262-004US
410. After a
August 2006