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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 62. PHY Autoscan Registers ($ Port Index + Offset)
Register
"PHY Control ($ Port Index + 0x60)"
"PHY Status ($ Port Index + 0x61)"
"PHY Identification 1 ($ Port Index + 0x62)"
"PHY Identification 2 ($ Port Index + 0x63)"
"Auto-Negotiation Advertisement ($ Port Index + 0x64)"
"Auto-Negotiation Link Partner Base Page Ability ($ Port
Index + 0x65)"
"Auto-Negotiation Expansion ($ Port Index + 0x66)"
"Auto-Negotiation Next Page Transmit ($ Port Index +
0x67)"
Reserved
Table 63. Global Status and Configuration Registers ($ 0x500 - 0X50C)
Register
"Port Enable ($0x500)"
"Interface Mode ($0x501)"
"Link LED Enable ($0x502)"
Reserved
"MAC Soft Reset ($0x505)"
"MDIO Soft Reset ($0x506)"
Reserved
"CPU Interface ($0x508)"
"LED Control ($0x509)"
"LED Flash Rate ($0x50A)"
"LED Fault Disable ($0x50B)"
"JTAG ID ($0x50C)"
Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 1 of 2)
Register
"RX FIFO High Watermark Port 0 ($0x580)"
"RX FIFO High Watermark Port 1 ($0x581)"
"RX FIFO High Watermark Port 2 ($0x582)"
"RX FIFO High Watermark Port 3 ($0x583)"
Reserved
"RX FIFO Low Watermark Port 0 ($0x58A)"
"RX FIFO Low Watermark Port 1 ($0x58B)"
"RX FIFO Low Watermark Port 2 ($0x58C)"
159
1
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RO
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RO
183
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RO
184
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184
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185
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RO
186
32
RO
187
32
RO
–
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32
R/W
188
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188
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R/W
189
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RO
–
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R/W
189
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R/W
190
32
RO
–
32
R/W
190
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R/W
190
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R/W
191
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191
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R
192
1
Bit Size
Mode
Ref Page
32
R/W
193
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RO
–
32
R/W
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R/W
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R/W
195
Document Number: 278757
Revision Date: 27-Oct-2005
Offset
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68 - 0x6F
Address
0x500
0x501
0x502
0x503 - 0x504
0x505
0x506
0x507
0x508
0x509
0x50A
0x50B
0x50C
Address
0x580
0x581
0x582
0x583
0x584 - 0x589
0x58A
0x58B
0x58C
Datasheet
Revision Number: 009
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