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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.3
Signal Description Tables
The I/O signals, power supplies, or ground returns associated with each IXF1104 MAC connection
ball are described in
Table 3.
SPI3 Interface Signal Descriptions (Sheet 1 of 8)
Signal Name
MPHY
TDAT31
TDAT30
TDAT29
TDAT28
TDAT27
TDAT26
TDAT25
TDAT24
TDAT23
TDAT22
TDAT21
TDAT20
TDAT19
TDAT18
TDAT17
TDAT16
TDAT15
TDAT14
TDAT13
TDAT12
TDAT11
TDAT10
TDAT9
TDAT8
TDAT7
TDAT6
TDAT5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TFCLK
39
Table 3
through
Table
Ball
Type
Designator
SPHY
TDAT7_3
F7
TDAT6_3
F5
TDAT5_3
G9
TDAT4_3
G8
Input
TDAT3_3
G7
TDAT2_3
G6
TDAT1_3
G5
TDAT0_3
G4
TDAT7_2
C8
TDAT6_2
F9
TDAT5_2
E10
TDAT4_2
E9
Input
TDAT3_2
E8
TDAT2_2
E7
TDAT1_2
E6
TDAT0_2
E5
TDAT7_1
H3
TDAT6_1
J3
TDAT5_1
J2
TDAT4_1
J1
Input
TDAT3_1
H1
TDAT2_1
G2
TDAT1_1
G1
TDAT0_1
F1
TDAT7_0
C6
TDAT6_0
B5
TDAT5_0
C5
TDAT4_0
C4
Input
TDAT3_0
D1
TDAT2_0
C3
TDAT1_0
C2
TDAT0_0
B3
TFCLK
D7
Input
14.
Standard
Description
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Clock.
TFCLK is the clock associated with all
3.3 V
transmit signals. Data and control lines are
LVTTL
sampled on the rising edge of TFCLK
(frequency operation range 90 - 133 MHz).
Bits
[31:24]
[7:0] for port 3
Bits
[23:16]
[7:0] for port 2
Bits
[15:8]
[7:0] for port 1
Bits
7:0]
[7:0] for port 0
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
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