Intel IXF1104 Datasheet page 40

Table 3. SPI3 Interface Signal Descriptions (Sheet 2 of 8)
Signal Name
MPHY
TPRTY_0
TENB_0
TERR_0
TSOP_0
TEOP_0
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Type
Designator
SPHY
TPRTY_0 D5
TPRTY_1 G3
Input
TPRTY_2 B9
TPRTY_3 J6
TENB_0 B7
TENB_1 E2
Input
TENB_2 C9
TENB_3 J4
TERR_0 A8
TERR_1 K1
Input
TERR_2 E11
TERR_3 J8
TSOP_0 C7
TSOP_1 E3
Input
TSOP_2 C10
TSOP_3 J5
TEOP_0 A7
TEOP_1 F3
Input
TEOP_2 E4
TEOP_3 H5
Standard Description
Transmit Parity.
TPRTY indicates odd parity for the TDAT
bus. TPRTY is valid only when a channel
asserts either TENB or TSX. Odd parity is
the default configuration; however, even
parity can be selected (see
3.3 V
Transmit and Global Configuration
LVTTL
($0x700)" on page
32-bit Multi-PHY mode: TPRTY_0 is the
parity bit covering all 32 bits.
4 x 8 Single-PHY mode: TPRTY_0:3 bits
correspond to the respective TDAT[3:0]_n
channels.
Transmit Write Enable.
TENB_0:3 asserted causes an attached
PHY to process TDAT[n], TMOD, TSOP,
TEOP and TERR signals.
3.3 V
32-bit Multi-PHY mode: TENB_0 is the
LVTTL
enable bit for all 32 bits.
4 x 8 Single-PHY mode: TENB_0:3 bits
correspond to the respective TDAT[3:0]_n
channels and their associated control and
status signals.
Transmit Error.
TERR indicates that there is an error in the
current packet. TERR is valid when
simultaneously asserted with TEOP and
TENB.
3.3 V
LVTTL
32-bit Multi-PHY mode: TERR_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TERR_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Transmit Start-of-Packet.
TSOP indicates the start of a packet and is
valid when asserted simultaneously with
TENB.
3.3 V
32-bit Multi-PHY mode: TSOP_0 is the bit
LVTTL
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TSOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Transmit End-of-Packet.
TEOP indicates the end of a packet and is
valid when asserted simultaneously with
TENB.
3.3 V
32-bit Multi-PHY mode: TEOP_0 is the bit
LVTTL
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TEOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Table 146 "SPI3
213).
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