Table of Contents
Advertisement
The SPI3 interface supports the following two modes of operation:
•
MPHY or 32 bit mode (one 32-bit data bus)
•
SPHY or 4 x 8 mode (four individual 8-bit data buses)
5.2.1
MPHY Operation
The MPHY operation mode is selected when bit 21 of
($0x700)"
Data Path
The IXF1104 MAC SPI3 interface has a single 32-bit data path in the MPHY configuration mode
(see
Figure
32-bit data bus would support only one IXF1104 MAC.
To support variable-length packets, the RMOD[1:0]/TMOD[1:0] signals are defined to specify
valid bytes in the 32-bit data bus structure. Each double-word must contain four valid bytes of
packet data until the last double-word of the packet transfer, which is marked with the end of
packet REOP/TEOP signal. This last double-word of the transfer contains up to four valid bytes
specified by the RMOD[1:0]/TMOD[1:0] signals.
The IXF1104 MAC port selection is performed using in-band addressing. In the transmit direction,
the network processor device selects an IXF1104 MAC port by sending the address on the
TDAT[1:0] bus marked with the TSX signal active and TENB signal inactive. All subsequent
TDAT[1:0] bus operations marked with the TSX signal inactive and the TENB active are packet
data for the specified port.
In the receive direction, the IXF1104 MAC specifies the selected port by sending the address on
the RDAT[1:0] bus marked with the RSX signal active and RVAL signal inactive. All subsequent
RDAT[1:0] bus operations marked with RSX inactive and RVAL active are packet data from the
specified port.
Note: See
Table 17 "SPI3 MPHY/SPHY Interface" on page 59
signals. The control signals with the port designator for Port 0 are the only ones used in MPHY
mode and they apply to all 4 ports.
provides a comprehensive list of SPI3 signal descriptions.
5.2.1.1
SPI3 RX Round Robin Data Transmission
The IXF1104 MAC uses a round-robin protocol to service each of the 4 ports dependent upon the
enable status of the port and if there is data available to be taken from the RX FIFO. The round
robin order goes from port 0, port 1, port 2, port 3, and back to port 0. A port is skipped and the
next port is serviced if it has no available transmit data. The data transfer bursts are user-
configurable burst lengths of 64, 128, or 256 bytes. The IXF1104 MAC also has a configurable
pause interval between data transfer bursts on the receive side of the interface. The RX SPI3 burst
lengths and the pause interval can be set in the
5.2.2
MPHY Logical Timing
The SPI3 interface AC timing for MPHY can be found in
Specifications" on page
associated with MPHY mode.
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
is set to 0 and bit 7 of the
"SPI3 Receive Configuration ($0x701)"
13). The bus interface is point-to-point (one output driving only one input load), so a
Table 3 "SPI3 Interface Signal Descriptions" on page 39
137. Logical timing in the following diagrams illustrates all signals
the"SPI3 Transmit and Global Configuration
for a complete list of the MPHY mode
"SPI3 Receive Configuration
Section 7.2, "SPI3 AC Timing
is set to 1.
($0x701)").
84
Advertisement
Table of Contents
