Ipg Receive Time 1 ($ Port_Index + 0X0A); Ipg Receive Time 2 ($ Port_Index + 0X0B); Ipg Transmit Time ($ Port_Index + 0X0C); Datasheet - Intel IXF1104 Datasheet

4-port gigabit ethernet media access controller
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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)
Name
IPG Receive Time 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)
Name
IPG Receive Time 2
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 79. IPG Transmit Time ($ Port_Index + 0x0C)
Name
IPG Transmit Time
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
165
Description
This timer is used during half-duplex operation
when there is a packet waiting for
transmission from the MAC. This timer starts
after CRS is de-asserted. If CRS is asserted
during this time, no transmission is initiated
and the counter restarts once CRS is de-
asserted again.
The value specified in this register is
calculated as follows: (register_value * 8) =
RXIPG1 in terms of bit times. Therefore, a
default value of 8 gives the following: (8 * 8 =
64 bit times for the default).
Description
This is only used in half-duplex operation. It
starts counting at the same time as RXIPG1.
Once RXIPG1 expires, a frame is transmitted
when RXIPG2 expires regardless of the CRS
value. If CRS is asserted before RXIPG1
expires, no transmission occurs and both
RXIPG1 an RXIPG2 are reset once CRS is
de-asserted again.
The value specified in this register is
calculated as follows: (register_value +5) * 8 =
RXIPG2 in terms of bit times. Therefore, a
default of 7 gives the following:
(7+5) * 8 = 96 bit times for default.
Description
This is a 10-bit value configuring IPG time for
back-to-back transmissions.
The value specified in this register is
calculated as follows: (register_value +4) * 8 =
TXIPG in terms of bit times. Therefore, a
default value of 8 gives the following:
(8+4) * 8 = 96 bit times for the default.
1
Address
Type
Default
Port_Index
R/W
0x00000008
+ 0x0A
1
Address
Type
Default
Port_Index
R/W
0x00000007
+ 0x0B
1
Address
Type
Default
Port_Index
R/W
0x00000008
+ 0x0C

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

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