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Intel 82543GC Specification Update

Gigabit ethernet controller
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82543GC Gigabit Ethernet Controller
Specification Update
June 18, 2004
Revision 2.1
The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate
from published specifications. Current characterized errata are documented in this Specification Update.
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Summary of Contents for Intel 82543GC

  • Page 1 Specification Update June 18, 2004 Revision 2.1 The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    TNCRS Statistic Register Has Live Count in Full-Duplex Mode...16 Receive IP Checksum Offload Disabled...16 EEPROM Initializes Software Defined Pins Incorrectly ...16 Continuous XOFFs Transmitted When Receive Buffer Is Full ...17 Default Speed Selection May Depend on EEPROM Presence...17 82543GC Gigabit Ethernet Controller Specification Update...
  • Page 4 82543GC Gigabit Ethernet Controller Specification Update Link Status Change Interrupt Only Occurs If Link is Up ...17 Early Transmit Feature Does Not Operate Correctly...17 TDO Output Not Floated When JTAG TAP Controller Inactive ...18 Initialization Ignores Incorrect EEPROM Signature...18 Internal Loopback Difficulties...18 Collision Pin Not Ignored in TBI Mode...18...

  • Page 5: Revision History

    82543GC Gigabit Ethernet Controller Specification Update REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Date of Revision Revision Description June 18, 2004 Initial Public Release...
  • Page 6 82543GC Gigabit Ethernet Controller Specification Update Note: This page is intentionally left blank.

  • Page 7: Preface

    Errata are design defects or errors. Errata may cause 82543GC device behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 8: General Information

    82543GC Gigabit Ethernet Controller Specification Update GENERAL INFORMATION This section covers the 82543GC device. 82543GC COMPONENT MARKING INFORMATION Stepping S- Spec Number Number Q415 S L3N8 Q416 S L3N9 Q417 The legend for the manufacturing code is as follows: YY = Assembly input year...

  • Page 9: Summary Table Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed 82543GC steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 10 82543GC Gigabit Ethernet Controller Specification Update NoFix Default Speed Selection May Depend on EEPROM Presence NoFix Link Status Change Interrupt Only Occurs If Link is Up NoFix Early Transmit Feature Does Not Operate Correctly NoFix TDO Output Not Floated When JTAG TAP Controller Inactive...

  • Page 11: Specification Changes

    Problem: When the 82543GC device initiates a PCI cycle to access data, it is possible for the target to issue a “retry”. A retry is a target disconnect without data transfer. In response, the 82543GC controller may attempt another read or write cycle to a different address instead of retrying the same memory location.

  • Page 12: Some Registers Cannot Be Accessed During Reset

    See Documentation Change #3. 5. DAC Accesses May Be Interpreted Incorrectly Problem: When the 82543GC device is mapped to a 64-bit PCI address space as a target device, it does not always handle dual-address cycle (DAC) accesses correctly. Implication: The 82543GC Gigabit Ethernet Controller is designed to function with addresses above the 4 GByte PCI boundary and can advertise this capability in base address register 0.

  • Page 13: Bit Preambles Sent In 10Mb And 100Mb Operation

    Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 9. CRS Detection Takes Too Long in MII Half-Duplex Mode Problem: When the 82543GC controller is operated in half-duplex mode, it can take up to 16 bit times to detect Carrier Sense (CRS) assertion. Implication: The IEEE specification is 8 bit times.

  • Page 14: Zero-Byte Pci Bus Writes

    13. Zero-Byte PCI Bus Writes Problem: The 82543GC Gigabit Ethernet Controller can generate zero-byte writes on a 32-bit PCI bus because it is has a 64-bit internal architecture. A zero-byte access is defined as a data transfer with IRDY# and TRDY# asserted but none of the byte enables asserted.

  • Page 15: Flash Memory Address Conflicts

    Workaround: None. Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 19. Transmit Packet Corruption of Small Packets Problem: When the 82543GC Ethernet Controller is transmitting and receiving simultaneously, it is possible that short packets will be corrupted before transmission.

  • Page 16: Receive Packet Loss In 100Mb Half-Duplex Operation

    82543GC Gigabit Ethernet Controller Specification Update When the size of a received packet exceeds the space in the packet buffer memory, the 82543GC Gigabit Ethernet Controller will drop the packet. This behavior is normal and is not affected by the erratum.

  • Page 17: Continuous Xoffs Transmitted When Receive Buffer Is Full

    When the controller is sending continuous XOFFs, it cannot transmit any data packets in the transmit FIFO. Workaround: Set up a watchdog timer in the software driver to monitor that packets given to the 82543GC device are actually transmitted. If packet transmission is not acknowledged after 2-3 seconds, the host system should be notified to reset the Ethernet controller.

  • Page 18: Tdo Output Not Floated When Jtag Tap Controller Inactive

    None. Do not use the early transmit function. Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. Documentation will change to remove text referring to this feature and its associated registers.

  • Page 19: Receive Descriptor Writeback Problems For Packets Spanning Multiple Buffers

    Implication: The 82543GC controller can receive frames up to the size of the receive packet buffer without difficulty. If the 82543GC controller locks up due to an oversize packet, a full software or hardware reset is needed. Workaround: Driver software should ensure that a minimum of 16K is allocated to the receive FIFO.

  • Page 20: Bus Initialization With Some Chipsets

    REQ64# is sampled low (asserted), the controller starts up with a 64-bit bus width. The PCI Local Bus Specification calls for 0 ns. minimum input hold time on this signal. However, the 82543GC controller requires 1 ns. input hold time.

  • Page 21: Specification Clarifications

    0x420 – 0x440), receive descriptor registers, diagnostic packet buffer head/tail registers (incorrect offset range 0x8000 – 0x8018) and the flow control threshold registers (incorrect offset range 0x160 – 0x168). Offsets for these registers will change in documentation to reflect the correct 82543GC device values. Refer to the following table for specific changes.

  • Page 22: Auto Speed Detect Function Requires Ctrl.slu Bit To Be Set

    Setting the Set Link Up (SLU) bit is a prerequisite for the Auto Speed Detect Enable (ASDE) bit in the Device Control Register to operate correctly. Asserting CTRL.SLU does not actually force link-up unless the link indication input indicates that the 82543GC device is connected to a PHY device with valid link. Documentation will change to explain the complete behavior.

  • Page 23: Register Summary Uses Improper Page Reference Format

    5. Register Summary Uses Improper Page Reference Format Problem: The 82543GC Register Summary refers to page numbers in the format (11-182, 11-186, 11-188, …) and (10- 162, 10-166, 10-166, …). The pagination will change to the format (182, 186, 188, …) and (162, 166, 186, …). The actual page numbers are correct.

  • Page 24: Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (Tbt)

    12.6 Reset should change. Note: Erratum #14 prohibits using TCP segmentation regardless of the preemption function. Affected Docs: OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual Rev. 2.01. 10. Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (TBT) Problem: The controller does not have the capability to control transmit burst length for Gigabit half-duplex operation through register programming.

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