Optical Module And I 2 C Ac Timing Specification; I 2 C Interface Timing; Bus Timing Diagram; Write Cycle Diagram - Intel IXF1104 Datasheet

®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.7 Optical Module and I
2
7.7.1 I C Interface Timing
Figure 45 and
AC timing characteristics.
Figure 45. Bus Timing Diagram
2
I C_Clk
2
I C_Data In
2
I C_Data Out
Figure 46. Write Cycle Diagram
2
I C_Clk
2
I C_Data
2
Table 53. I C AC Timing Characteristics (Sheet 1 of 2)
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
147
2
C AC Timing Specification
Figure 46 illustrate bus timing and write cycle, and
t
F
t
LOW
t t
HD.STA SV.SAT
t
AA
8th
ACK
BIT
WORD n
Parameter
Clock frequency, SCL
Clock pulse width low
Clock pulse width High
Noise suppression
Clock low to data valid out
Time the bus must be free before a new transmission starts
Start hold time
Table 53
t
HIGH
t
LOW
t t
HD.DAT SU.DAT
t
DH
t WR (1)
STOP START
CONDITION CONDITION
2
shows the I C Interface
t
R
t
SU.STO
t
BUF
Min Max Units
- 100 kHz
4.7 µs
4.0 µs
100 µs
0.1 4.5 µs
4.7 - µs
4.0 - µs

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005