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Figure 23. SerDes Receiver Jitter Tolerance
Note: UI = Unit interval.
5.6.2.6
Transmit Jitter
The SerDes core total transmit jitter, including contributions from the intermediate frequency PLL,
is comprised of the following two components:
•
A deterministic component attributed to the SerDes core's architectural characteristics
•
A random component attributed to random thermal noise effects
Since the thermal noise component is random and statistical in nature, the SerDes core total
transmit jitter must be specified as a function of BER.
5.6.2.7
Receive Jitter
The SerDes core total receiver jitter, including contributions from the intermediate frequency PLL,
is comprised of the following two components:
•
A deterministic component attributed to the SerDes core architectural characteristics
•
A random component attributed to random thermal noise effects.
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
16 ui
10+1
0
10-1
0
1
2
10
10
10
Sinusoidal Jitter Mask
375 Hz 16 ui
22.5836 kHz 8.5 ui
1.9195 MHz 0.1 ui
3
4
5
10
10
10
Frequency
6
7
10
10
B0745-02
106
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