Timing Specifics; Tx_Er And Rx_Er Coding; Rgmii Signal Definitions; Tx_Er And Rx_Er Coding Description - Intel IXF1104 Datasheet

4-port gigabit ethernet media access controller
Table of Contents

Advertisement

®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.4.2

Timing Specifics

The IXF1104 MAC RGMII complies with RGMII Rev1.2a requirements.
timing specifics.
5.4.3

TX_ER and RX_ER Coding

To reduce interface power, the transmit error condition (TX_ER) and the receive error condition
(RX_ER) are encoded on the RGMII interface to minimize transitions during normal network
operation (refer to
definitions for RGMII.
Table 27. RGMII Signal Definitions
IXF1104
MAC Signal
TXC_0:3
TD[3:0]_n
TX_EN
RXC_0:3
RD[3:0]_n
RX_DV
The value of RGMII_TX_ER and RGMII_TX_EN are valid at the rising edge of the clock while
TX_ER is presented on the falling edge of the clock. RX_ER coding behaves in the same way (see
Table
28,
Figure
Table 28. TX_ER and RX_ER Coding Description
Condition
Receiving valid frame,
no errors
Receiving valid frame,
with errors
Receiving invalid frame
(or no frame)
Transmitting valid frame,
no errors
Transmitting valid frame
with errors
Transmitting invalid
frame (or no frame)
NOTE: Refer to
97
Table 28 on page 97
for the encoding method).
RGMII
Standard
Source
Signal
Depending on speed, the transmit reference clock is 125 MHz, 25
TXC
MAC
MHz, or 2.5 MHz +/– 50ppm.
Contains register bits 3:0 on the rising edge of TXC and register bits
TD<3:0>
MAC
7:4 on the falling edge of TXC.
TXEN is on the leading edge of TXC.
TX_CTL
MAC
TX_EN xor TX_ER is on the falling edge of TXC.
Continuous reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50
RXC
PHY
ppm.
Contains register bits 3:0 on the leading edge of RXC and register bits
RD<3:0>
PHY
7:4 on the trailing edge of RXC.
RX_DV is on the leading edge of RXC.
RX_CTL
PHY
RX_DV or RXERR is the falling edge of RXC.
19, and
Figure
20).
RX_DV = true
Logic High on rising edge of RXC
RX_DV = true
Logic High on rising edge of RXC
RX_DV = false
Logic Low on rising edge of RXC
TX_EN = true
Logic High on rising edge of TXC
TX_EN = true
Logic High on rising edge of TXC
TX_EN = false
Logic Low on rising edge of TXC
Figure 19
for TX_CTL behavior, and
Table 27
Table 27
Description
Description
RX_ER = false
Logic High on the falling edge of RXC
RX_ER = true
Logic Low on the falling edge of RXC
RX_ER = false
Logic Low on the falling edge of RXC
TX_ER =false
Logic High on the falling edge of TXC
TX_ER = true
Logic Low on the falling edge of TXC
TX_ER = false
Logic low on the falling edge of TXC
Figure 20
for RX_CTL behavior.
provides the
provides signal

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

Advertisement

Table of Contents
loading

Table of Contents