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Intel 21555 User Manual

Non-transparent pci-to-pci bridge
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21555 Non-Transparent PCI-to-
PCI Bridge
User Manual
July 2001
Order Number: 278321–002

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Summary of Contents for Intel 21555

  • Page 1 21555 Non-Transparent PCI-to- PCI Bridge User Manual July 2001 Order Number: 278321–002...
  • Page 2 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    Indirect I/O Transaction Generation...42 4.4.2 Subtractive Decoding of I/O Transactions ...44 Configuration Accesses ...44 4.5.1 Type 0 Accesses to 21555 Configuration Space ...44 4.5.2 Initiation of Configuration Transactions by 21555...45 21555 Bar Summary ...47 PCI Bus Transactions...49 Transactions Overview ...49...
  • Page 4 Prefetchable Read Transactions Using the 64-bit Extension ... 57 5.4.4 Read Performance Features and Tuning Options ... 57 64-Bit and 32-Bit Transactions Initiated by the 21555 ... 59 Target Terminations... 60 5.6.1 Target Terminations Returned by the 21555 ... 60 5.6.2...
  • Page 5 16.4.1 Primary and Secondary Address ...130 16.4.2 Configuration Transaction Generation Registers...140 16.5 PCI Registers...147 16.5.1 Configuration Registers ...147 16.5.2 Primary and Secondary Command Registers...149 16.5.3 Device-Specific Control and Status Registers ...156 16.6 I2O Registers ...165 21555 Non-Transparent PCI-to-PCI Bridge User Manual Contents...
  • Page 6 Lookup Table Entry Format ... 41 10 Dual-Address Transaction Forwarding ... 42 11 CompactPCI Hot-Swap Connections ... 73 12 21555 Hot-Swap Insertion and Removal ... 75 13 Synchronous Secondary Clock Generation... 78 14 Parallel and Serial ROM Connections ... 84 15 PROM Read Timing ...
  • Page 7 13 Delayed Write Transaction Target Termination Returns ...55 14 Delayed Read Transaction Target Termination Returns ...56 15 Prefetch Boundaries ...58 16 21555 Transaction Ordering Rules... 62 17 Power Management, Hot-Swap, and Reset Signals...65 18 Reset Mechanisms ...67 19 Power Management Actions...71 20 Primary and Secondary PCI Bus Clock Signals ...77...
  • Page 8 103 Primary Set IRQ and Secondary Set IRQ Registers ... 173 104 Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers... 174 105 Primary Set IRQ Mask and Secondary Set IRQ Mask Registers ... 174 106 Scratchpad 0 Through Scratchpad 7 Registers... 174 21555 Non-Transparent PCI-to-PCI Bridge User Manual...
  • Page 9 127 Bypass Register...191 128 Boundary-Scan Register...191 129 Boundary Scan Order ...191 130 Vital Product Data (VPD) ECP ID and Next Pointer Register...192 131 Vital Product Data (VPD) Address Register ...193 132 VPD Data Register ...193 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 11: Preface

    Provides an overview of the 21555 functionality and architecture. Describes PCI signal pins grouped by function. Contains details about how addresses are decoded. Describes how the 21555 implements the theory of operation about PCI transactions. Describes the reset operation and initialization requirements.

  • Page 12: Cautions And Notes

    The range may be enclosed in [square brackets] as well. • The left number is upper limit of the range. • The right number is the lower limit of the range. For example: Primary byte offset: 13:10h. Bytes Bits 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 13: Signal Nomenclature

    Signal Nomenclature 21555 device signal names are printed in lowercase type. Prefixes and suffixes are tagged with a leading or trailing letter and are delimited with an “_” underscore: • The prefix “p_” denotes a primary bus signal. For example: p_ad is the primary interface address/data bus.

  • Page 14: Register Abbreviations

    Read. Write from secondary interface only. Primary bus writes have no effect. R/(WP) Read. Write from primary interface only. Secondary bus writes have no effect. Upstream configuration address. Upstream configuration data. Upstream I/O address. Upstream I/O data. W1TL Write 1 to load. Description 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 15: Introduction

    The 21555 operates at 3.3 V, but is also 5.0-V I/O tolerant. Adapter cards designed for the 21555 can be keyed as a PCI universal card edge connector, permitting use in either a 5-V or 3-V slot.

  • Page 16: 21555 Intelligent Controller Application

    Since the 21555 is non transparent, the device driver for the add-in card must be aware of the presence of the 21555 and manage its resources appropriately. The 21555 allows the entire subsystem to appear as a single virtual device to the host.

  • Page 17: 21555 And Ppb Feature Comparison

    Table 3 shows compares a 21555 and to a transparent PPB. Table 3. 21555 and PPB Feature Comparison Feature Transaction forwarding Address decoding Address translation Configuration time resources Clocks Secondary bus central functions 21555 Non-Transparent PCI-to-PCI Bridge User Manual Non-Transparent PPB or 21555 Transparent PPB •...

  • Page 18: Architectural Overview

    ROM interface control logic for both serial and parallel ROM connections (interfaces between the ROM registers and ROM signals). • Secondary PCI bus arbiter interface to secondary bus device request and grant lines, as well as the 21555 secondary master control logic. •...

  • Page 19: 21555 Microarchitecture

    Primary Target Control Primary Master Control JTAG JTAG Signals 21555 Non-Transparent PCI-to-PCI Bridge User Manual Downstream Delayed Buffer Downstream Posted Write Buffer Upstream Read Data Buffer Downstream Read Data Buffer Upstream Posted Write Buffer Upstream Delayed Buffer Device- Primary...

  • Page 20: Special Applications

    Bits not decoded. The 21555 cannot be enabled as a snooping agent on the primary bus. This is because the 21555 cannot guarantee that it can buffer and forward all palette writes, since the 21555 has finite buffer space and no backoff mechanism when snooping.

  • Page 21: Transaction Forwarding

    Enabling VGA decoding in both directions. Refer to subtractive I/O decoding in the previous bullet. Again, there is the case of a non translated I/O address decoded by the 21555 on both interfaces as a target and forwarded to the opposite interface.

  • Page 23: Signal Descriptions

    Arbitration Interrupt Error Test Access Port 21555 Non-Transparent PCI-to-PCI Bridge User Manual describes the PCI signal groups, function, and provides a page reference. Description All PCI pins required by the PCI Local Bus Specification, Revision 2.2. All PCI 64-bit extension pins required by the PCI Local Bus Specification, Revision 2.2.

  • Page 24: Primary Pci Bus Interface Signals

    As an initiator of a transaction on the primary bus, the 21555 looks for the assertion of p_devsel_l within five clock cycles of p_frame_l assertion; otherwise, the 21555 terminates the transaction with a master abort.
  • Page 25 The device receiving data samples p_par as an input to check for possible parity errors. When the primary PCI bus is idle, the 21555 drives p_par to a valid logic level when p_gnt_l is asserted (one clock cycle after the p_ad bus is parked).

  • Page 26: Primary Pci Bus Interface 64-Bit Extension Signals

    Primary PCI interface address and data upper 32 bits. The 21555 does not bus park these pins. These pins are tristated during the assertion of p_rst_l. Signals p_ad[63:32] are driven to a valid value when the 64-bit extension is disabled (p_req64_l is deasserted during p_rst_l assertion).
  • Page 27 Description Primary PCI interface upper 32 bits parity. The 21555 does not bus park this pin. This pin is tristated during the assertion of p_rst_l. Signal p_par64 is driven to a valid value when the 64-bit extension is disabled (p_req64_l is deasserted during p_rst_l assertion).

  • Page 28: Secondary Pci Bus Interface Signals

    When the secondary PCI bus is idle, the 21555 drives s_ad to a valid logic level when its secondary bus grant is asserted. Secondary PCI interface command and byte enables. These signals are a multiplexed command field and byte enable field.
  • Page 29 The device receiving data samples s_par as an input to check for possible parity errors. When the secondary PCI bus is idle, the 21555 drives s_par to a valid logic level when its secondary bus grant is asserted (one clock cycle after the s_ad bus is parked).

  • Page 30: Secondary Pci Bus Interface 64-Bit Extension Signals

    Secondary PCI interface address and data upper 32 bits. The 21555 does not bus park these pins. These pins are tristated during the assertion of s_rst_l. Signals s_ad[63:32] are driven to a valid value when the 64-bit extension is disabled (s_req64_l is deasserted during s_rst_l assertion).

  • Page 31: Miscellaneous Signals

    Description Secondary PCI interface upper 32 bits parity. The 21555 does not bus park this pin. This pin is tristated during the assertion of s_rst_l. Signal s_par64 is driven to a valid value when the 64-bit extension is disabled (s_req64_l is deasserted during s_rst_l assertion).

  • Page 33: Address Decoding

    The system and local address maps are independent of each other. The 21555 supports address translations between the two address maps when forwarding transactions upstream or downstream. Note: When enabled as a target, the 21555 ignores any transactions that it initiates as a master with the exception of type 0 configuration transactions.

  • Page 34: Csr Address Decoding

    Address Decoding CSR Address Decoding The 21555 implements a set of CSRs that are mapped in memory or in I/O space. The registers are mapped independently on the primary and secondary interfaces. The following BARs are used for CSR mapping: •...

  • Page 35: Using The Bar Setup Registers

    All downstream and upstream BARs have programmable sizes, and can be disabled so that they request no space. The Primary CSR and Downstream Memory 0 BAR cannot be totally disabled, as the 21555 CSRs are always mapped in the bottom 4KB. The forwarding part of the range can be disabled by requesting only 4KB of memory Table 12 on page 47 summarizes the minimum and maximum range for each address range).

  • Page 36: Direct Address Translation

    Note that since transactions addressing the bottom 4 KB of the Primary CSR and Downstream Memory 0 BAR are targeted at the 21555 CSRs, no forwarding and therefore no address translation is performed. Direct address translation is used for transactions in that range above the low 4 KB boundary.

  • Page 37: Lookup Table Based Address Translation

    4.3.2, Upstream Memory 2 address translation is treated differently than the other ranges. The 21555 uses a page size based lookup table to perform address translation for transactions falling into this range. A lookup table provides a flexible way of translating secondary bus local addresses to primary bus system addresses.

  • Page 38: Upstream Memory 2 Window Size

    [22:17] [31:24] [23:18] [31:25] [24:19] [31:26] [25:20] [31:27] [26:21] [31:28] [27:22] [31:29] [28:23] [31:30] [29:24] [31] [30:25] 21555 Non-Transparent PCI-to-PCI Bridge User Manual Offset (bits) [7:0] [8:0] [9:0] [10:0] [11:0] [12:0] [13:0] [14:0] [15:0] [16:0] [17:0] [18:0] [19:0] [20:0] [21:0]...

  • Page 39: Address Translation Using A Lookup Table

    The lookup table is implemented on-chip and no external memory is needed. The lookup table is part of the memory space that the 21555 requests with its Primary CSR Memory BAR and Secondary CSR Memory BAR. The lookup table is also indirectly accessible in I/O or memory space at offsets 24h and 28h.

  • Page 40: Lookup Table Entry Format

    For writes, the 21555 discards memory write data and asserts s_serr_l, when the SERR# Disable for Master Abort during Posted Write bit is 0. For reads, the 21555 returns FFFFFFFFh on reads if the Master Abort Mode bit is 0, or returns a target abort if the Master Abort Mode bit is a 1.

  • Page 41: Forwarding Of 64-Bit Address Memory Transactions

    Forwarding of 64 The 21555 considers the host and local memory space above the 4 GB boundary to be shared. This means that the 21555 uses a flat address map in this space. Dual-address cycle (DAC) transactions are used for addressing above the 4 GB boundary.

  • Page 42: I/O Transaction Address Decoding

    I/O Transaction Address Decoding The 21555 provides a mechanism where one BAR on each interface can be configured to be an I/O BAR instead of a memory BAR. The Downstream I/O or Memory 1 BAR in primary configuration space is used to decode primary bus I/O transactions for forwarding to the secondary bus.
  • Page 43 I/O transaction sequence. When the bit reads as a 1, the initiator should not proceed until a subsequent read of the own bit returns a 0 (zero). The 21555 automatically sets the own bit to a 1after it is read from the primary interface.

  • Page 44: Subtractive Decoding Of I/O Transactions

    The 21555 responds as a target to Type 0 configuration transactions on both its primary and secondary interfaces when the IDSEL pin for that interface is asserted. The 21555 is a single function device so it does not decode the function number.

  • Page 45: Initiation Of Configuration Transactions By 21555

    I/O transaction to initiate the transaction. The 21555 uses the same byte enables that the initiator used to read or write the register. The 21555 responds to the access of the Upstream or Downstream Configuration Data register with a target retry until the access is completed on the target bus.
  • Page 46 When the bit reads as a one, the initiator should not proceed until a subsequent read of the own bit returns a 0 (zero). The 21555 automatically sets the own bit to a 1 after it is read.

  • Page 47: 21555 Bar Summary

    21555 Bar Summary Table 12 shows a summary of the 21555 BARs. Table 12. Bar Summary Primary CSR and Downstream Memory 0 Primary CSR I/O Secondary CSR Memory Secondary CSR I/O Primary Expansion ROM Downstream I/O or Memory 1 Downstream Memory 2...

  • Page 49: Pci Bus Transactions

    Section 5.6, “Target Terminations” on page • Section 5.7, “Ordering Rules” on page Transactions Overview The 21555 responds to transactions using these commands as a target on both interfaces. The 21555 does not respond to transactions using any other PCI commands. • All memory commands.

  • Page 50: Posted Write Transactions

    5.2.2. The 21555 does not initiate a memory write transaction on the target bus until at least a cache line amount of data is posted. When the transaction consists of less than a cache line, the 21555 waits until the entire burst is posted. For all posted write behavior dependent on the cache line size (CLS), the 21555 uses the cache line value corresponding to the target interface.

  • Page 51: Memory Write Transactions

    The 21555 disconnects an MWI on a cache line boundary when less than a cache line remains free in the posted write buffer. This is a different queue full disconnect behavior than that used for the memory write command. In this case, alignment is preserved at the expense of maximizing burst length.

  • Page 52: 64-Bit Extension Posted Write Transaction

    The 21555 continues the MWI transaction as long as a full cache line is posted in the posted write queue. A a full cache line corresponds to the cache line size of the target bus. When the 21555 is within one data phase of delivering a complete cache line and there is not another full cache line posted in the queues, the 21555 master terminates the transaction at the cache line boundary.
  • Page 53 5.2.4.3 Write-Through When the 21555 is able to obtain access to the target bus and start transferring write data to the target before the transaction has been terminated on the initiator bus, it automatically enters flow-through mode. In flow-through mode, the 21555 can sustain long write bursts as long as a queue-empty condition is detected in posted write buffers or until an aligned disconnect boundary is reached.

  • Page 54: Delayed Write Transactions

    CSR write access that causes the 21555 to initiate an I/O write transaction. When an I/O write intended for the opposite PCI bus is first initiated, the 21555 returns a target retry. When the delayed transaction queue is not full and if a transaction having the same address and bus command does not already exist in the delayed transaction queue, the 21555 queues the transaction information: •...

  • Page 55: Delayed Read Transactions

    Target abort Master abort When the 21555 has a delayed completion to return to an initiator, and the initiator does not repeat the transaction before the Master Time-Out Counter for that interface expires, it discards the delayed completion transaction. When enabled to do so, the 21555 asserts SERR# on the initiator bus. The Master Time-Out Counter expiration...

  • Page 56: Nonprefetchable Reads

    See Section 5.7. When the transaction is a nonprefetchable read as described in requests only a single Dword of data. When the transaction is a memory read, the 21555 follows the prefetch rules outlined in Section 5.4.2. The 21555 completes the transaction on the target bus and adds the read data and parity to the read data queue and the completion status to the delayed transaction queue.

  • Page 57: Prefetchable Reads

    When the master terminates the transaction, the 21555 discards the unconsumed read prefetch data. Read data is discarded at a rate of 8 Dwords per clock cycle. During read data discard, the 21555 is unable to return any other delayed transaction completions on the initiator bus or enqueue new delayed requests.

  • Page 58: Prefetch Boundaries

    However, limited flow-through minimizes the latency when returning read data with a 2:1 bandwidth mismatch. When the read data queue empties while the 21555 is in limited flow-through mode, the 21555 waits up to seven cycles and then disconnects if read data is still not available.

  • Page 59: 64-Bit And 32-Bit Transactions Initiated By The 21555

    5.4.4.3 Read Queue Full Threshold Tuning The 21555 implements read queue management control bits for each read data queue in the Chip Control 1 configuration register. These bits specify at what read-queue threshold the 21555 initiates a delayed prefetchable read transaction on the target bus. Use of these bits can minimize fragmentation of prefetchable read bursts. The encoding and behavior of these bits are as follows: •...

  • Page 60: Target Terminations

    Multiple data phases requested by the initiator for an I/O or configuration access. • Low two address bits of the transaction are non-zero. The 21555 returns a target abort and sets the Signaled Target Abort bit in the Primary and Secondary Status register under the following circumstances: •...

  • Page 61: Transaction Termination Errors On The Target Bus

    5.6.2 Transaction Termination Errors on the Target Bus When the 21555 detects a target abort on the target bus, the 21555 sets the Received Target Abort in the Primary and Secondary Status register. See Table 62, “Primary and Secondary Status Registers” on page the 21555: •...

  • Page 62: Transaction Ordering Rules

    Posted writes are delivered in the order in which they are accepted. Delayed transactions may be initiated by the 21555 in any order, and are not necessarily initiated in the order in which they are received. When the 21555 initiates a delayed transaction, the 21555 can do the following: •...
  • Page 63 Note: Performance may be affected if the Delayed Transaction Order Control bit is set, as the 21555 deasserts the PCI request signal between transactions. When the Delayed Transaction Order Control bit is zero, the 21555 may keep REQ# asserted after a target retry or target disconnect if another transaction is pending. See Delayed completions are returned to the initiator when ready, regardless of the order in which corresponding delayed requests were queued.

  • Page 65: Initialization Requirements

    If the PME# isolation circuitry is needed, it must be implemented externally. Primary PCI bus RST#. Signal p_rst_l forces the 21555 to a known state. All register state is cleared, and all PCI bus outputs are tristated, with the exception of s_ad, s_cbe_l, and s_par if the 21555 is designated as the central function.

  • Page 66: Reset Behavior

    Reset Behavior The 21555 implements a primary reset input, p_rst_l, a secondary reset input s_rst_in_l, and a secondary reset output, s_rst_l. The 21555 also implements a Chip Reset bit and a Secondary Reset bit in the Control Register” on page 188.

  • Page 67: Reset Mechanisms

    When set automatically, the Secondary Reset bit also clears automatically and s_rst_l deasserts after greater than 100 s following s_rst_l assertion. Assertion of s_rst_l by setting the secondary reset bit does not cause the 21555 register state to be reset. However, all the 21555 data buffers are reset.

  • Page 68: Central Function During Reset

    Central Function During Reset The 21555 is selected to be the secondary bus central function when it detects pr_ad[6] low when s_rst_l is asserted. When the 21555 detects this condition, it immediately drives s_ad, s_cbe_l, and s_par low and tristates secondary bus control signals for the duration of secondary bus reset.

  • Page 69: With Srom, Local, And Host Processors

    A SROM is supported, but not required, for the 21555 preinitialization. In the case where a SROM is not connected to the 21555 or when the first data bits read does not contain 10b, the 21555 terminates the SROM read and configuration space is then available for local processor configuration.

  • Page 70: Without Local Processor

    6.3.5 Without Host Processor Initialization of the 21555 can be performed without a host processor. In this case, the local processor must perform the initialization of the primary configuration registers from the secondary interface. Power Management Support The 21555 implements the PCI Power Management interface on behalf of the subsystem.

  • Page 71: Transitions Between Power Management States

    6.4.1 Transitions Between Power Management States The 21555 is put into a different power state by writing the Power State bits in the Power Management Control and Status configuration register. Table 19 states. Although any transition to a lower power state is allowed, all transitions to a higher power state must go to Table 19.

  • Page 72: Power Management Data Register

    A Data Select field in the Power Management Control and Status register selects the type of data to be reported. A Data Scale register provides the scale factor for this data. The 21555 allows implementation of this Data register for static data reporting for the subsystem. The Data Scale value and eight possible data values are loaded into the 21555 through the SROM preload operation.

  • Page 73: Insertion And Removal Process

    The state of the micro-switch controls the state of the LED in the Local Reset state. As long as the micro-switch is closed in this state, pulling l_stat high, the LED is on. the 21555 does not drive l_stat in this state.
  • Page 74 Initialization Requirements The 21555 enters the Signal Insertion state from the Serial Preload state when the following conditions are satisfied: • Serial preload is complete. • Primary Lockout Reset Value bit cleared. • Ejector handle is closed (micro-switch opens, and l_stat is sampled low).

  • Page 75: 21555 Hot-Swap Insertion And Removal

    When the INS_STAT bit is cleared, the card is ready for normal operation. When l_stat continues to be sampled low, that indicates that the ejector handle is closed (and the micro-switch is open), meaning the card remains fully inserted. The 21555 enters the Normal Operation state. Figure 12. 21555 Hot...
  • Page 76 When the 21555 enters the Signal Removal state, the REM_STAT bit is set and p_enum_l is asserted to indicate that a removal request is being made. Since the card is not yet ready for removal, the 21555 drives l_stat low in this state to force the LED off.

  • Page 77: Clocking

    When the 21555 operates in synchronous mode, p_clk and s_clk must operate at the same frequency and have a fixed phase relationship. Operation in synchronous mode saves at least one clock cycle of latency for transactions crossing the bridge.

  • Page 78: 21555 Secondary Clock Outputs

    13. When s_clk_o is used for secondary bus devices, one of the externally buffered clock outputs must be used for the 21555 secondary clock input, s_clk. This clock output is a buffered version of p_clk and therefore has the same clock frequency as p_clk. An exception is when the primary bus is operating at 66 MHz and the secondary bus operates at 33 MHz, then the 21555 divides s_clk_o by 2 to generate a 33 Mhz clock (See Signal s_clk_o is disabled and driven low when the 21555 samples pr_ad[5] low during reset.

  • Page 79: 66 Mhz Support

    The 21555 pulls s_m66ena low when the primary bus is operating at 33 MHz (p_m66ena low) and s_clk_o is enabled. When s_clk_o is enabled, it is assumed that the 21555 is controlling the clocking of the secondary bus and since s_clk_o is a buffered version of p_clk, it must operate at 33 MHz.

  • Page 81: Parallel Rom Interface

    PROM registers. The 21555 supports the attachment of a standard PROM or EPROM with the addition of a small amount of external logic. Flash ROMs compatible with Intel’s 28F00x can be used with this interface. The 21555 supports a PCI expansion ROM BAR on its primary interface with ROM sizes of 4KB to 16MB.

  • Page 82: Prom Interface Signals

    When the preload sequence 10b is not detected during the first read, the serial ROM preload is terminated after the first two bits are read and the 21555 registers remain at their reset values. This is not actually sampled at reset, but during the first serial ROM read.
  • Page 83 PROM chip select or device ready. For a single device attachment, pr_cs_l is used for the PROM chip select. The 21555 asserts pr_cs_l low after the address is shifted out and demultiplexer through the three external octal registers. The 21555 deasserts pr_cs_l according to the access time specified in the Register”...

  • Page 84: Parallel And Serial Rom Connection

    Parallel and Serial ROM Connection Figure 14 shows how a parallel and serial ROM can be connected to the 21555. This figure illustrates the connection of a 16MB ROM. When a smaller ROM is used, the address registers corresponding to the upper address bits can be eliminated, as those upper address bits are ignored.

  • Page 85: Prom Read Timing

    When a byte read of the PROM is performed, the 21555 follows this sequence on the ROM interface, also shown in Figure 1. The 21555 drives address bits [23:16] on the pr_ad[7:0] pins and asserts pr_ale_l to enable the address registers.

  • Page 86: Prom Write By Csr Access

    4. When the initiator reads the PROM Start bit in the is complete. When a byte write to the PROM is performed, the 21555 follows this sequence on the ROM interface, also shown Figure 1. The 21555 drives address bits [23:16] on the pr_ad[7:0] pins and asserts the address register enable, pr_ale_l.

  • Page 87: Prom Dword Read

    The 21555 performs four consecutive byte reads of the ROM. When the four byte reads are complete, the 21555 returns the read data to the initiator on the next read attempt to that address to complete the delayed transaction.

  • Page 88: Access Time And Strobe Control

    Access Time and Strobe Control The 21555 controls both the access time and the read and write strobe timing through the ROM Setup CSR. The access time is specified as a multiple of the p_clk signal and must be set to 8, 16, 64, or 256 times the length of a p_clk cycle when p_clk is operating at 33 MHz or below, and 16, 32,128, or 512 times the length of a p_clk cycle when p_clk is operating above 33 MHz.

  • Page 89: Attaching Additional Devices To The Rom Interface

    Attaching Additional Devices to the ROM Interface The 21555 allows additional devices to be attached to the ROM interface. Two ROM interface signals are slightly redefined to support multiple devices by setting the Multiple Device Enable bit in the Chip Control 0 configuration register.

  • Page 90: Attaching Multiple Devices On The Rom Interface

    8-bit register 8-bit register 8-bit register pr_clk 21555 Non-Transparent PCI-to-PCI Bridge User Manual Serial sr_cs sr_ck sr_di sr_do Parallel d[7:0] W E # O E # a[7:0] a[15.8] a[20:16] C E#...

  • Page 91: Serial Rom Interface

    Once reset is complete, the 21555 automatically starts a serial read from the ROM by detecting that p_rst_l and s_rst_l are deasserted and the Chip Reset bit reset to 0 (zero). All of the 21555 initialization data is loaded with a single read operation by keeping the chip select asserted and toggling the clock.

  • Page 92: Srom Configuration Data Preload Format

    — Write operations always consist of 8 data bits. For a read type operation, the data is driven from the SROM to the 21555 on signal sr_do. For a write operation, the data is driven from the 21555 to the SROM on signal sr_di.
  • Page 93 CSR access and return a ready indication to clear the SROM_POLL bit. The SROM is polled by the 21555 when the SROM Start bit is written with a 1 when the SROM_POLL bit is set. The 21555 asserts sr_cs and drives sr_di (pin pr_ad[1]) low. When the SROM drives sr_do (pin pr_ad[2]) high in response, it has completed the operation internally and the 21555 clears the SROM_POLL bit.

  • Page 94: Srom Write All Timing Diagram

    (sr_ck) sr_cs pr_ad[1] (sr_di) pr_ad[2] (sr_do) Figure 20. SROM Write Enable Timing Diagram pr_ad[0] (sr_ck) sr_cs pr_ad[1] (sr_di) Figure 21. SROM Write Disable Timing Diagram pr_ad[0] (sr_ck) sr_cs pr_ad[1] (sr_di) 21555 Non-Transparent PCI-to-PCI Bridge User Manual A7476-01 A7477-01 A7478-01...

  • Page 95: Srom Check Status Timing Diagram

    Figure 22. SROM Erase Timing Diagram pr_ad[0] pr_ad[1] Figure 23. SROM Erase All Operation pr_ad[0] (sr_ck) sr_cs pr_ad[1] (sr_di) Figure 24. SROM Check Status Timing Diagram 21555 Non-Transparent PCI-to-PCI Bridge User Manual (sr_ck) sr_cs (sr_di) pr_ad[0] (sr_ck) sr_cs pr_ad[2] busy (sr_di)

  • Page 97: Arbitration

    Arbitration This chapter describes the arbitration signals. It also describes how the 21555 implements primary and secondary PCI bus arbitration. See Chapter 16 10.1 Primary PCI Bus Arbitration Signals Table 23 describes the primary PCI bus arbitration signals. Table 23. Primary PCI Bus Arbitration Signals...

  • Page 98: Primary Pci Bus Arbitration

    When a prefetchable read is ongoing on the primary bus when another delayed read is queued behind it, the 21555 delays the assertion of p_req_l. The assertion of p_req_1 is delayed until the 21555 is ensured that there is room in the read data queue for the second delayed read transaction.

  • Page 99: Secondary Arbiter Example

    Arbiter Control Register = 1000000111b Each bus master, including the 21555, may be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the Arbiter Control register in device-specific configuration space.

  • Page 100: Secondary Bus Arbitration Using An External Arbiter

    Arbitration The 21555’s internal arbiter may be programmed to park the secondary PCI bus either at the last master to use the bus, or always on the 21555. In the former case, an initiator's secondary bus grant remains asserted unless and until another initiator has asserted its secondary bus request.

  • Page 101: Interrupt And Scratchpad Registers

    Interrupt and Scratchpad Registers This chapter presents the theory of operation information about the 21555 interrupt handling and about the 32-bit scratchpad registers. See Chapter 16 11.1 Primary and Secondary PCI Bus Interrupt Signals describes the primary and secondary PCI bus interrupt signals.
  • Page 102 A power management transition from state D1 or D2 to state D0 occurs. — Cleared by writing a 1 to the corresponding status bit in the Chip Status CSR. — Asserts s_inta_l when the corresponding mask bit is zero. 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 103: Doorbell Interrupts

    (four in all) if desired. These registers can be accessed from the primary or secondary interface of the 21555, in either memory space or I/O space. The 21555 doorbell interrupt functionality consists of the following registers: •...

  • Page 105: Error Handling

    Error Handling This chapter presents the theory of operation information about the 21555 Error handling capability. See for specific information about the Error registers. 12.1 Error Signals This section describes both the primary and secondary PCI bus error signals. 12.1.1...

  • Page 106: Secondary Pci Bus Error Signals

    Secondary PCI interface SERR#. Signal s_serr_l can be driven low by any device on the secondary bus to indicate a system error condition. The 21555 also samples s_serr_l as an input and conditionally forwards it to the primary bus on p_serr_l. The 21555 can conditionally assert s_serr_l for the following reasons: •...

  • Page 107: Parity Errors

    Parity Errors The 21555 checks, forwards, and generates parity on both the primary and secondary buses. When forwarding transactions, the 21555 forwards the data parity condition as queued, whether it is bad parity or good parity. Table 29 describes the 21555’s responses to parity errors.
  • Page 108 • Asserts s_perr_l when returning s_trdy_l to initiator on secondary bus (for both CSR and BAR forwarding mechanisms). — | The 21555 is returning data, all action is taken by initiator. — • Returns read data with bad parity to initiator (for both CSR and BAR forwarding mechanisms).
  • Page 109 — | 1 • Sets secondary Data Parity Detected bit. • Asserts s_perr_l. — | The 21555 is returning data, all action is taken by initiator. — • Writes the data normally. — | 0 • Sets the secondary Parity Error Detected bit.

  • Page 110: System Error (Serr#) Reporting

    The 21555 has two system error pins. Signal p_serr_l reports system errors on the primary interface, and s_serr_l reports system errors on the secondary interface. For the 21555 to assert the SERR# signal for that interface, the SERR# Enable must be set in the Command Configuration register corresponding to that interface. In addition, each device-specific condition has a disable bit for each interface.

  • Page 111: Jtag Test Port

    This chapter presents the theory of operation information about the 21555 JTAG interface. See specific information about the JTAG registers. The 21555’s implementation of the JTAG test port is according to IEEE Std. 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture.

  • Page 112: Test Access Port Controller

    Synchronously after five tck clock cycles, with tms held high. Figure 26. Signal trst_l States Note: Prior to normal 21555 operation, this signal must be strobed low or pulled low with a 1k resistor. 26). While signal trst_l is low, the test access port controller enters the...

  • Page 113: I2O Support

    This chapter presents the theory of operation information about the 21555 I20 support. See information about I20 registers. The 21555 implements an I2O messaging unit to allow passing of I2O messages between the host system and the local subsystem which is called IOP in I2O nomenclature.
  • Page 114 Inbound Free_List as described in the following paragraph. When the 2 Dword buffer is empty, the 21555 treats a read to location 44h as a delayed memory read transaction. The address that the 21555 uses to initiate the transaction on the secondary bus is the current value of the Outbound Post_List Head Pointer.

  • Page 115: Outbound Message Passing

    31of the Outbound Free_List counter to a zero, causing the 21555 to decrement the Outbound Free_List counter by 1. The 21555 does not use the value of this counter internally, but makes this function available to track the number of empty MFAs in the Outbound Free_List When the local processor posts a message to the Outbound Post_List, it must write bit 31 of the Outbound Post_List Counter to a zero, which causes the 21555 to increment the counter by 1.

  • Page 116: Notes

    MFAs from the Outbound Post_List as described in the following paragraph. When the 2 Dword buffer is empty, the 21555 treats a read to location 44h as a delayed memory read transaction. The address that the 21555 uses to initiate the transaction on the secondary bus is the current value of the Outbound Post_List Head Pointer.
  • Page 117 • All MFA counters maintained by the 21555 may be individually loaded with any data value by writing a 1 to bit 31 of the corresponding counter Dword offset. When either the Inbound Free_List Counter or the Outbound Post_List Counter is loaded, the 21555 discards any prefetched data in the corresponding prefetch buffer.

  • Page 119: Vpd Support

    1. The VPD address and VPD Flag bits are written. This requires a write to bytes E7:E6h, where the low 9 bits carry the VPD byte address and bit 15 is a 0 (zero), indicating a read operation. The 21555 adds the VPD base address, 080h, to the VPD byte address to obtain the serial ROM address and perform a read of 4 bytes.

  • Page 120: Writing Vpd Information

    3. The VPD Flag bit is polled. When the 21555 returns a 0, the write is complete. When a write is attempted to a location in the first 1Kb of serial ROM space (address bits 8:7 is 00b), the 21555 does not perform the write operation and clears the flag bit immediately.

  • Page 121: List Of Registers

    Chapter 15, “VPD Support” 16.1 Register Summary This chapter lists the 21555 configuration space registers and the CSR address map registers. A description of the notes used in the tables used in this chapter are listed as follows: • Byte offsets that are specific to the primary or secondary interfaces are followed by a (P) or (S) respectively.

  • Page 122: Configuration Registers

    Register Name (Hex) 1011 B555 0000 0290 Device dependent 068000 00000001 000000000 000000000 00000000 00000000 00000000 0000 21555 Non-Transparent PCI-to-PCI Bridge User Manual Write Read Preload Access Access — — — — — Secondary — — — [6] Y [7,3:0]...
  • Page 123 23:20 (S) 67:64 (P) Reserved 27:24 (S) 73:70 (P) Reserved 33:30 (S) 7C(P) Primary and Secondary Interrupt 3C (S) Line Registers, page 154 21555 Non-Transparent PCI-to-PCI Bridge User Manual Reset Value Register Name (Hex) 0000 00000000 000000 00000000 0000 0290 068000...
  • Page 124 Indeterminate Indeterminate Indeterminate Indeterminate 0000 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate FFFFF000 00000000 00000000 00000000 00000000 00000000 21555 Non-Transparent PCI-to-PCI Bridge User Manual Write Read Preload Access Access — — Primary — Primary Primary — Secondary Second — Secondary Primary —...
  • Page 125 VPD Next Ptr Vital Product Data (VPD) Address Register, page 193 E7:E6 VPD Address VPD Data Register, page 193 EB:E8 VPD Data 21555 Non-Transparent PCI-to-PCI Bridge User Manual Reset Value Register Name (Hex) 00000000 00000000 0y00 y = 0 or 4...

  • Page 126: Control And Status Registers

    Downstream I/O Address Reset Value Register Name (Hex) 00x1000b 00000000 Register Name Reset Value Indeterminate Indeterminate Indeterminate Indeterminate 0000 Indeterminate 21555 Non-Transparent PCI-to-PCI Bridge User Manual Write Read Preload Access Access — Secondary — — — Write Access Read Access Primary...
  • Page 127 I20 Inbound Free Head Pointer I2O Inbound Post_List Tail Pointer, page 04F:04C I20 Inbound Post Tail Pointer I2O Outbound Free_List Tail Pointer, page 053:050 I20 Outbound Free Tail Pointer 21555 Non-Transparent PCI-to-PCI Bridge User Manual Register Name Reset Value Indeterminate Indeterminate Indeterminate 0000...
  • Page 128 Upstream Page Boundary IRQ 1 Register Name Reset Value Indeterminate 00000000 00000000 00000000 00000000 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0000 FFFF FFFF 00000000 00000000 21555 Non-Transparent PCI-to-PCI Bridge User Manual Write Access Read Access Secondary Secondary Secondary Secondary W1TC W1TS W1TC W1TC W1TC...
  • Page 129 ROM Address Register, page 178 0CE:0CC ROM Address ROM Control Register, page 178 ROM Control Generic Own Bits Register, page 0D2:0D0 164Generic Own Bits 21555 Non-Transparent PCI-to-PCI Bridge User Manual Register Name Reset Value FFFFFFFF FFFFFFFF 0000 0000 0000 0000...

  • Page 130: Address Decoding

    • Primary byte offset: 13:10h • Secondary byte offset: 53:50h The Primary CSR and Downstream Memory 0 BARs map the 21555 registers into primary memory space. They can specify a downstream memory range for forwarding of memory transactions. To specify a downstream forwarding range, load the Downstream Memory 0 Setup Register from the optional SROM or the local processor This load must occur before configuration software running on the host processor can access this register.

  • Page 131: Secondary Csr Memory Bars

    • Primary byte offset: 13:10h • Secondary byte offset: 53:50h The Primary CSR and Downstream Memory 0 BARs map the 21555 registers into primary memory space. They can specify a downstream memory range for forwarding of memory transactions. To specify a downstream forwarding range, load the Downstream Memory 0 Setup Register from the optional SROM or the local processor This load must occur before configuration software running on the host processor can access this register.

  • Page 132: Primary And Secondary Csr I/O Bars

    Name Space Indicator Reserved 31:8 Base Address The Primary and Secondary CSR I/O BARs map the 21555 registers into primary and secondary I/O space, respectively. (Sheet 2 of 2) Description Indicates if this space is prefetchable. • When a 0, do not use prefetching when reading the 21555 registers.

  • Page 133: Downstream I/O Or Memory 1 And Upstream I/O Or Memory 0 Bar

    Name Space Indicator Type Prefetchable — 31:6 Base Address 21555 Non-Transparent PCI-to-PCI Bridge User Manual Downstream I/O or Memory 1 BAR 1B:18h 5B:58h Description • When a 0, this BAR is disabled or memory space is requested memory space. • When a one (1), I/O space is requested.

  • Page 134: Downstream Memory 2 And 3 Bar, And Upstream Memory 1 Bar

    These registers are similar and are described together. These registers define address ranges in which memory transactions on the primary interface of the 21555 are forwarded to the secondary interface for the downstream BARs, and in which memory transactions on the secondary interface are forwarded to the primary interface for the upstream BAR.

  • Page 135: Upper 32 Bits Downstream Memory 3 Bar

    13:4 — 31:14 Base Address 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description This register defines the upper 32 bits of a memory range for downstream forwarding of memory transactions. The lower 32 bits are contained in the Downstream Memory 3 BAR. These bits are used to indicate the size of the requested address range and to set the base address of the range.

  • Page 136: Downstream I/O Or Memory 1 And Upstream I/O Or Memory 0 Translated Base Register

    The remaining bits may be written but are ignored when performing address translation. When an I/O or memory transaction is initiated by the 21555 on the target bus, the original base address is replaced with the value contained in this register.

  • Page 137: Downstream Memory 0, 2, 3, And Upstream Memory 1 Translated Base Register

    The remaining bits can be written but are ignored when performing address translation. When a memory transaction is initiated by the 21555 on the target bus, the original base address is replaced with the value contained in this register. List of Registers...

  • Page 138: Downstream I/O Or Memory 1 And Upstream I/O Or Memory 0 Setup Registers

    • When 0, the corresponding BAR is disabled and reads as 0. R/(WS) • When 1, the corresponding BAR is enabled, with size and type specified by this setup register. • Reset value is 0 21555 Non-Transparent PCI-to-PCI Bridge User Manual Upstream I/O or Memory 0 Setup C7:C4h C7:C4h...

  • Page 139: Downstream Memory 0, 2, 3, And Upstream Memory 1 Setup Registers

    Bit [31] of the Downstream Memory 0 Setup register always reads as 1, indicating that the BAR cannot be disabled. When a bus master attempts to write this bit with a 0, the 21555 returns all bits {31:12] of the setup register as 1s (request 4KB).

  • Page 140: Configuration Transaction Generation Registers

    Configuration Transaction Generation Registers All of these registers are mapped into the 21555 configuration space and described in 21555 initiates a transaction only when the Configuration Data registers are accessed at these locations using I/O reads and writes. The Downstream Configuration Data Register and the Upstream Configuration Data Register are treated as reserved registers for all memory accesses.

  • Page 141: Downstream And Upstream Configuration Address Registers

    Primary byte Secondary byte CSR Space Name CFG_ADDR 31:0 (CA) 21555 Non-Transparent PCI-to-PCI Bridge User Manual Downstream Configuration Address 83:80h 83:80h (Reserved) 003:000h Description This register contains the address for a configuration transaction to be generated on the target bus. The address is driven exactly as written in this register.

  • Page 142: Downstream Configuration Data And Upstream Configuration Data Registers

    Configuration Data registers are not owned. When read as a 0 from the primary interface, this bit is subsequently set to a 1 by the 21555 when the Downstream Configuration Control bit is a 1. R0TS (P) • When 1, a master owns Downstream Configuration Address and R(S) Downstream Configuration Data registers.

  • Page 143: Configuration Csr

    Enables the 21555 to perform downstream indirect configuration transactions. • When 0, the 21555 will not initiate a configuration transaction on the secondary interface when the Downstream Configuration Data register is accessed. The Downstream Configuration Data register is treated as a reserved register.

  • Page 144: Downstream I/O Address And Upstream I/O Address Registers

    Enables the 21555 to perform upstream indirect configuration transactions. • When 0, the 21555 will not initiate a configuration transaction on the primary interface when the Upstream Configuration Data register is accessed. The Upstream Configuration Data register is treated as a reserved register.

  • Page 145: Downstream I/O Data And Upstream I/O Data Registers

    • When 0, downstream I/O Address and Downstream I/O Data registers are not owned. When read as a 0 from the primary interface, this bit is subsequently set to a 1 by the 21555. R0TS (P) • When 1, downstream I/O Address and Downstream I/O Data R (S) registers are owned by a master.

  • Page 146: Lookup Table Offset Register

    Data registers are owned by a master. Enables the 21555 to perform downstream indirect I/O transactions. • When 0, the 21555 will not initiate a I/O transaction on the secondary interface when the Downstream I/O Data register is accessed. The Downstream I/O Data register is treated as a reserved register.

  • Page 147: Pci Registers

    Configuration Registers The registers described in this section are shared between the primary and secondary interfaces. 21555 Non-Transparent PCI-to-PCI Bridge User Manual are registers that provide a method for the lookup table to be accessed using I/O writable; byte enables are ignored.

  • Page 148: Primary Interface Configuration Space Address Map

    The Vendor ID identifies Intel as the vendor of this device and is internally hardwired to be 8086 hex. Description Device ID identifies this device as the 21555 and is internally hardwired to be B555h. 21555 Non-Transparent PCI-to-PCI Bridge User Manual Primary...

  • Page 149: Primary And Secondary Command Registers

    Controls the response of the 21555 when a parity error is detected on the corresponding interface. • When 0, the 21555 does not assert PERR#, nor does it set the Data Parity Reported bit in the appropriate Primary or Secondary Status registers.

  • Page 150: Primary And Secondary Status Registers

    Product derivatives hardcode this to either 0 or 1. Reserved. Returns 0 when read. Back Reads as 1 to indicate that the 21555 is able to respond to fast back back transactions on the corresponding interface. 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 151: Revision Id (Rev Id) Register

    Reads as 01b to indicate that the 21555 responds no slower than with medium timing. This bit is set to a 1 when the 21555 is acting as a target on the corresponding bus and returns a target abort to the initiator.

  • Page 152: Primary And Secondary Class Code Registers

    Dwords. Used for prefetching memory reads and for terminating MWIs. Valid cache line sizes are 8, 16, and 32 Dwords. When the cache line size is set to any other value, the 21555 uses the same behavior as when the cache line size is set to 8.

  • Page 153: Primary Latency And Secondary Master Latency Timer Registers

    BiST register. The default value of this register is 00h after reset assertion, which indicates that BiST is not supported. However, after reset the 21555 allows this field to be automatically preloaded with a value from the serial ROM (when attached) or programmed via the secondary interface by the local process •...

  • Page 154: Subsystem Vendor Id Register

    34h and 74h Description Pointer to the first set of ECP registers. Returns DCh to indicate that the first set of ECP registers begins at configuration offset DCh. For the 21555, this points to the Power Management registers. Reset value is DCh...

  • Page 155: Primary And Secondary Interrupt Pin Registers

    (ML) 21555 Non-Transparent PCI-to-PCI Bridge User Manual Primary Interrupt Pin Description This register indicates which PCI interrupt pin the 21555 uses on the corresponding bus. This is a read read indicating that the 21555 uses INTA#. Primary Minimum Grant Description...

  • Page 156: Device-Specific Control And Status Registers

    FFFFFFFFh if a read. For posted writes, SERR is not asserted on the initiator bus. • When 1, the 21555 returns a target abort in response to a delayed transaction. For posted writes, SERR will be asserted (if otherwise enabled) on the initiator bus.
  • Page 157 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description Sets the maximum number of PCI clock cycles that the 21555 waits for an initiator on the secondary bus to repeat a delayed transaction request. The counter starts when the delayed transaction completion is ready to be returned to the initiator.
  • Page 158 This bit can be written from the secondary interface only. The local processor must write this bit to a 0 to allow the 21555 to be configured by the host processor, unless preloaded to 0 by serial ROM.
  • Page 159 21555 discards the transaction. • When 1, all 2 retry counters are disabled and do not place any limits on the number of attempts the 21555 makes when initiating a posted write or delayed transaction. • Reset value is 0...

  • Page 160: Chip Control 1 Register

    Description Controls the queue full threshold limit of the downstream posted write queue. When the queue is designated full, the 21555 returns retry to posted writes on the primary bus. Otherwise, the 21555 accepts write data into the posted write queue.
  • Page 161 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description Controls subtractive decoding for downstream and upstream I/O transactions. When the 21555 is enabled to perform subtractive decoding in one direction, those transactions are forwarded to the opposite bus with no address translation.

  • Page 162: Chip Status Register

    Inbound Post or Outbound Free list; Reads remove an entry from the Inbound Free or Outbound Post list. • Reset value is 0. Selects the I20 FIFO size. The 21555 supports the following values: • 000b : 256 entries • 001b : 512 entries •...
  • Page 163 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description This bit is set to a 1 and p_serr_l is conditionally asserted when the 21555 discards a downstream posted write transaction after receiving target retries from the secondary bus target (Retry counters must R/W1TC not be disabled).

  • Page 164: Generic Own Bits Register

    Table 80. Generic Own Bits Register The 21555 implements two generic own bits that can be accessed in either memory or I/O space from either the primary or secondary interface. These bits may be used as an aid to lock resources in software. When a bus master reads the Own bit, it returns 1 if it has already been set, or it returns 0 if the Own bit is available and then automatically sets the bit upon completion of the read.

  • Page 165: I2O Registers

    (unless it is asserted for other reasons). • When 1, the Outbound Post_List is not empty. When the Outbound Post_List Interrupt Mask bit is zero, the 21555 asserts p_inta_l as long as this status bit is set. • Reset value is 0 Reserved.

  • Page 166: I2O Inbound Post_List Interrupt Mask

    When this register is read from the primary bus, the 21555 returns the value from the head of the I2O inbound Free_List. When this register is written from the primary bus, the 21555 writes the data to the tail of the inbound R/(WP) Post_List.

  • Page 167: I2O Inbound Free_List Head Pointer

    Name Reserved Outbound Post 31:2 Head Ptr 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description Reserved. Returns 0 when read. Specifies the local memory Dword address of the Inbound Free_List Head Pointer. Increments when the I2O Inbound Queue at offset 40h is read on the primary bus.

  • Page 168: I2O Inbound Post_List Counter

    [31] of this register is written with a 0 during the same write. R/(WS) When bit [31] is written with a 1, the 21555 loads the counter with the value written. Decrements when the Inbound Queue at offset 40h is read from the primary interface, except when the counter is zero.

  • Page 169: I2O Outbound Post_List Counter

    [31] of this register is written with a 0 during the same write. R/(WS) When bit [31] is written with a 1, the 21555 loads the counter with the value written. Decrements when the Outbound Queue at offset 44h is read from the primary interface, except when the counter is zero.

  • Page 170: Interrupt Registers

    When the Chip IRQ Mask bit for this R/W1TC event is a 0, the 21555 asserts p_inta_l to indicate to the host system that this signal was deasserted. Writing a 1 clears this bit to a 0. Writing a 0 has not effect.

  • Page 171: Chip Clear Irq Mask Register

    PAGE0_IRQ 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description • When 0, signal s_inta_l is asserted on the 21555’s secondary interface when the corresponding chip event bit is a 1, indicating a return of power state to D0. • When 1, the corresponding chip event bit does not generate an interrupt.

  • Page 172: Upstream Page Boundary Irq 1 Register

    Upstream Memory 2 range. Bit 0 corresponds to the 33 page, and bit 31 corresponds to the 64 21555 sets the appropriate bit when it successfully transfers data to/ R/W1TC from the initiator that addresses the last Dword in a page.

  • Page 173: Primary Clear Irq And Secondary Clear Irq Registers

    These registers affect primary and secondary interrupts in the same way and are described together. Offsets Byte Name 15:0 SET_IRQ 21555 Non-Transparent PCI-to-PCI Bridge User Manual Primary Clear IRQ Secondary Clear IRQ 099:098h 09B:09Ah Description This register controls the state of the Primary or Secondary Interrupt Request bits.

  • Page 174: Scratchpad Registers

    Primary Clear IRQ Mask 0A1:0A0h Description • When 0, an interrupt is generated on the 21555’s primary or secondary interface when the corresponding Primary or Secondary Interrupt Request bit is a 1. • When 1, the corresponding interrupt request bit cannot generate an interrupt.

  • Page 175: Prom Registers

    This register defines an address range in which a memory read transaction on the primary interface of the 21555 results in a read access to the PROM interface. The Primary Expansion ROM Setup register controls the size of the address range requested by the Primary Expansion ROM Base Address register. The Primary Expansion ROM Setup register must be loaded either from the serial ROM or by the local processor before configuration software running on the host processor can access this register.

  • Page 176: Primary Expansion Rom Setup Register

    • When 1, the specified by this setup register. • Reset value is 0 Reserved. Returns 0 when read. 21555 Non-Transparent PCI-to-PCI Bridge User Manual only bit that always returns “Serial Preload is disabled and reads is enabled, with size...

  • Page 177: Rom Setup Register

    Table 110. ROM Data Register Byte Offsets: 0CAh Name ROM_DATA 21555 Non-Transparent PCI-to-PCI Bridge User Manual Description Number of p_clk cycles that pr_cs_l asserts low (in default mode) or pr_ale_l drives high (in multiple device mode) for a PROM or other external device access.

  • Page 178: Rom Address Register

    When the previous serial ROM operation was a write all, erase all, write, or erase, writing this bit causes the 21555 to poll the serial ROM to test for the completion of the operation. The result of the poll operation is reflected in bit 3 of this register.

  • Page 179: Srom Registers

    PROM read/write control bit. This bit may be written with the same CSR access that sets the PROM Start bit. • When 0, the 21555 performs a read of the PROM when the PROM Start bit is set to a 1.

  • Page 180: Serial Preload Sequence

    Indicates whether the secondary bus 64 • When 0, the secondary bus 64 • When 1, the secondary bus 64 Class Code 21555 Non-Transparent PCI-to-PCI Bridge User Manual bit extension is enabled. bit extension is disabled. bit extension is enabled.
  • Page 181 Upstream I/O or Memory 0 Setup [7:0]. Bits [5:4] are not loaded and should be 0. Upstream I/O or Memory 0 Setup [15:8] Upstream I/O or Memory 0 Setup [23:16] 21555 Non-Transparent PCI-to-PCI Bridge User Manual Class Code List of Registers...
  • Page 182 • [5:4] Power Management Control and Status [14:13] • [7:6] Power Management Capabilities Register [1:0] • [0] Power Management Capabilities Register [2] • [1] Power Management Capabilities Register [5] • [7:2] Power Management Capabilities Register [14:9] 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 183: Arbiter Control

    Controls whether the 21555 parks on itself or on the last master to use the bus. • When 0, during bus idle, the 21555 parks the bus on the last master to use the bus. • When 1, during bus idle, the 21555 parks the bus on itself. The bus grant is removed from the last master and internally asserted to the 21555.

  • Page 184: Primary Serr# Disable Register

    This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert p_serr_l for a particular condition. When the bit is a 0, the assertion of p_serr_l is not masked for this event.

  • Page 185: Init Registers

    2 primary bus target. Reset value is 0 Disables s_serr_l assertion when the 21555 detects a target abort on the primary interface in response to an upstream posted write. Reset value is 0 Disables s_serr_l assertion when the 21555 detects a master abort on the primary interface when initiating an upstream posted write.

  • Page 186: Power Management Capabilities Register

    Clock Required for PME# Assertion. Reads as 1 to indicate that a clock is required to assert PME#, when any of bits [15:11] in this register are asserted. Read as 0 when bits [15:11] are all 0, indicating that the 21555 does not assert PME#.

  • Page 187: Power Management Control And Status Register

    R/(WS) Reset value is 00b PME Status. The 21555 sets this bit to a 1 when s_pme_l is asserted and the PME# Support bit for the current power state is a 1. This corresponds to when the 21555 would normally assert p_pme_l, but regardless of the state of the PME_En bit.

  • Page 188: Reset Control Register

    Reset value is 00h Description Secondary bus reset. • When 0, the 21555 deasserts s_rst_l. This bit must be cleared by a configuration write when it is set by a configuration write. Otherwise, it clears automatically after 100 s or when p_rst_l deasserts.
  • Page 189 When REM STAT is high, l_stat is not tristated but continues to be driven by the 21555 (LED is off). • When 1, the 21555 drives l_stat high and the LED is forced on. • Reset value is 0...

  • Page 190: Jtag Registers

    JTAG 16.14 Registers This chapter presents the theory of operation information about the 21555 JTAG registers. See theory of operation information. Table 126. JTAG Instruction Register Options (Sheet 1 of 2) The 4-bit instruction register selects the test mode and features. The instruction codes are shown .

  • Page 191: Bypass Register

    When the value of a group disable control bit is 0, the output driver is enabled. When the value is 1, the driver is tri-stated. There are TBD groups of bi-directional drivers, and therefore TBD group disable control bits. 21555 Non-Transparent PCI-to-PCI Bridge User Manual Instruction Test Register...

  • Page 192: Vpd Registers

    VPD Enhanced Capabilities Port ID. Read only as 03h to identify these ECP registers as VPD registers. Pointer to next ECP registers. Reads as ECh to point to the next set of ECP registers, supporting CompactPCI Hot 21555 Non-Transparent PCI-to-PCI Bridge User Manual for theory of operation information. Swap.

  • Page 193: Vital Product Data (Vpd) Address Register

    [8:0]. Note that this operation is not necessarily Dword aligned. • When the write is complete, the 21555 sets this bit to a 0. Description VPD Data. Contains the VPD read or write data. For a read, this register should be read after a read operation was initiated and the 21555 has returned the VPD Flag bit to a 1.
  • Page 195 IPP – Integrated Performance Primitives • ISO – International Standards Organization • ITU – International Telecommunication Union • IXA – Internet Exchange Architecture; for example: Intel® IXA. • LMS – Least mean square • MB – Macroblock • MC – Motion compensation...
  • Page 196 Vdd _vio or V/IO – (S)scondary or (P)rimary_Voltage Input or Output. In PCI specifications it is defined as V/ • VGA – Video Graphics Adapter • VLD – Variable length decoding • Vss – Voltage for Substrate & Sources, usually ground potential. 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

  • Page 197: Index

    Delayed transaction data buffers 18 I/O 43 queues 44 subtractive decoding 44 target retry counter 45 Delayed write transactions 54 21555 Non-Transparent PCI-to-PCI Bridge User Manual Device ID 122 Domains processor 15 Doorbell interrupt functionality 103 Fast Back-to-Back 52 Features...
  • Page 198 Type 0 configuration header 15 Upstream base address register 34 Use of interrupt mask bits 101 Use of interrupt request status bits 101 Vendor ID 122 Voltage operating 15 Write performance tuning options Write flow-through 53 21555 Non-Transparent PCI-to-PCI Bridge User Manual...

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