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Table 24. Operational Mode Configuration Registers
Register Name
"Desired Duplex
($ Port_Index +
0x02)"
"MAC IF Mode
and RGMII
Speed ($
Port_Index +
0x10)"
"Port Enable
($0x500)"
"Interface Mode
($0x501)"
"Clock and
Interface Mode
Change Enable
Ports 0 - 3
($0x794)"
NOTE: The initialization sequence provided in
page 130
5.1.4
Fiber Mode
When the IXF1104 MAC is configured for fiber mode, the TX Data path from the MAC is an
internal
10-bit interface as described in the IEEE 802.3z specification. It is connected directly to an internal
SerDes block for serialization/deserialization and transmission/reception on the fiber medium to
and from the link partner.
The MAC contains all of the PCS (8B/10B encoding and 10B/8B decoding) required to encode and
decode the data. The MAC also supports auto-negotiation per the IEEE 802.3z specification via
access to the
and
"Diverse Config Write ($ Port_Index +
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Register
Address
0x002 – Port 0
The
"Desired Duplex ($ Port_Index + 0x02)" on page 163
whether a port is to be configured for full-duplex or half-duplex
0x082 – Port 1
operation.
0x102 – Port 2
NOTE: Half-duplex operation is only valid for 10/100 speeds where the
0x182 – Port 3
The
"MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" on
page 167
given port.
0x010 – Port 0
NOTE: Set the
0x090 – Port 1
0x110 – Port 2
0x190 – Port 3
0x500
Bit 0 – Port 0
Each
Bit 1 – Port 1
to 0x1 to enable a port. This should be the last step in the configuration
process for a port.
Bit 2 – Port 2
Bit 3 – Port 3
The
"Interface Mode ($0x501)"
copper (RGMII or GMII) line-side interface an integrated SerDes fiber
0x501
line-side interface.
Bit 0 – Port 0
For copper operation for a given port, set the relevant bit to 0x1.
Bit 1 – Port 1
For fiber operation for a given port, set the relevant bit to 0x0.
Bit 2 – Port 2
Bit 3 – Port 3
NOTE: All ports are configured for fiber operation in the IXF1104 MAC
The
"Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)"
0x794
indicates to an internal clock generator when to sample the new value
Bit 0 – Port 0
of the
"Interface Mode ($0x501)"
Bit 1 – Port 1
When any of these two configuration values are changed for a port, the
Bit 2 – Port 2
corresponding bits must be kept in this register under reset by writing
Bit 3 – Port 3
0x0 to the relevant bit.
must be followed for proper configuration of the IXF1104 MAC.
"TX Config Word ($ Port_Index +
Description
RGMII line interface has been selected.
determines the MAC operational frequency and mode for a
"Clock and Interface Mode Change Enable Ports 0 - 3
($0x794)" on page 221
to 0x0 prior to any change in the
register value. This ensures that a change in the MAC clock
frequency is controlled correctly. If the
Mode Change Enable Ports 0 - 3 ($0x794)"
correctly, the IXF1104 MAC may not be configured to the
proper mode.
"Port Enable ($0x500)"
bit relates to a port. Set the appropriate bit
selects whether a port operates with a
default mode of operation.
"MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)"
(copper/fiber).
Section 6.1, "Change Port Mode Initialization Sequence" on
0x17)",
"RX Config Word ($ Port_Index +
0x18)".
defines
"Clock and Interface
is not used
and the
0x16)",
76
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