Tx Fifo Register Overview; Tx Fifo High Watermark Ports 0 - 3 ($0X600 – 0X603); Datasheet - Intel IXF1104 Datasheet

®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.7

TX FIFO Register Overview

Table 132 through
FIFO High and Low watermark.
Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)
Name
TX FIFO High
Watermark Port 0
TX FIFO High
Watermark Port 1
TX FIFO High
Watermark Port 2
TX FIFO High
Watermark Port 3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
203
Table 139 provide an overview of the TX FIFO registers, which include the TX
Description
High watermark for TX FIFO Port 0. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
transfers to avoid an overflow condition.
High watermark for TX FIFO Port 1. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
transfers to avoid an overflow condition.
High watermark for TX FIFO Port 2. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
transfers to avoid an overflow condition.
High watermark for TX FIFO Port 3. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
transfers to avoid an overflow condition.
1
Address Type Default
0x600 R/W 0x000003E0
0x601 R/W 0x000003E0
0x602 R/W 0x000003E0
0x603 R/W 0x000003E0

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005