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Table 98. PHY Identification 2 ($ Port Index + 0x63)
Bit
Name
31:16
Reserved
15:10
PHY ID Number
9:4
Manufacturer's Model
Manufacturer's
3:0
Revision Number
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)
Bit
Name
31:16
Reserved
15
Next Page
14
Reserved
13
Remote Fault
12
Reserved
11
ASM_DIR
10
Pause
9
100BASE-T4
100BASE-TX
8
Full-Duplex
100BASE-TX
7
Half-Duplex
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Description
Reserved
The PHY identifier is composed of register bits
24:19 of the OUI (Organizationally Unique
Identifier)
Six bits containing the manufacturer's part number
Four bits containing the manufacturer's revision
number
Description
Reserved
0 =
1 = Manual control of Next Page (software)
Reserved
0 = No remote fault
1 = Remote fault
Reserved
Advertise Asymmetric Pause Direction register bit.
This register bit is used in conjunction with Pause
(Register bit 4.10)
0 = Link partner is not capable of asymmetric
pause
1 = Link partner is capable of asymmetric pause
Advertise to link partner that Pause operation is
desired (IEEE 802.3x Standard)
0 = 100BASE-T4 capability is not available
1 = 100BASE-T4 capability is available
The IXF1104 MAC does not support 100BASE-T4,
but allows this register bit to be set to advertise in
auto-negotiation sequence for 100BASE-T4
operation. If this capability is desired, an external
100BASE-T4 transceiver can be switched in.
0 = DTE is not 100BASE-TX, full-duplex mode
capable
1 = DTE is 100BASE-TX, full-duplex mode
capable
0 = DTE is not 100BASE-TX, half-duplex mode
capable
1 = DTE is 100BASE-TX, half-duplex mode
capable
1
Type
Default
0x001111001
00000000
RO
0
RO
011110
RO
010000
RO
0000
1
Type
Default
0x00000100
111100001
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
1
184
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