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®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
When the CRC Error Pass Filter bit = 0
takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast
packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0.
Table 22. CRC Errored Packets Drop Enable Behavior
CRC Error
1
Pass
1
0
0
0
1. See
Table 91 "RX Packet Filter Control ($ Port_Index + 0x19)" on page
2. See
Table 123 "RX FIFO Errored Frame Drop Enable ($0x59F)" on page
3. See
Table 147 "SPI3 Receive Configuration ($0x701)" on page
NOTE: x = "DON'T CARE"
5.1.1.4
CRC Error Detection
Frames received by the MAC are checked for a correct CRC. When an incorrect CRC is detected
on a received frame, the RX FCSError RMON statistic counter is incremented for each CRC
errored frame. Received frames with CRC errors may optionally be dropped in the RX FIFO (refer
to
Section 5.1.1.3.6, "Filter CRC Error Packets" on page
SPI3 interface and may be dropped by the switch or system controller.
Frames transmitted by the MAC are also checked for correct CRC. When an incorrect CRC is
detected on a transmitted frame, the TX CRCError RMON statistic counter is incremented for each
incorrect frame.
5.1.2
Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link
partner take a temporary "Pause" in packet transmission. This allows the requesting network node
to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its available
memory. The temporary pause allows the device to process packets already received or in transit,
thus freeing up the FIFO space allocated to those packets.
69
("RX Packet Filter Control ($ Port_Index +
RX FIFO Errored-
RERR
Frame Drop
Enable
2
Enable
x
x
0
1
0
0
1
x
Actions
3
When CRC Errored PASS = 1, CRC errored packets
are not filtered and are passed to the SPI3 interface.
They are not marked as bad, cannot be dropped, and
cannot be signaled with RERR.
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are signaled with an RERR to the
switch or Network Processor.
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are not signaled with an RERR.
CRC errored packets are marked as bad, dropped in
the RX FIFO, and never appear at the SPI3 interface.
NOTE: Packet sizes above the RX FIFO Transfer
Threshold (see
cannot be dropped in the RX FIFO and are
passed to the SPI3 interface. These packets
can optionally be signaled with RERR on the
SPI3 interface if the RERR Enable bit = 1.
172.
196.
215.
68). Otherwise, the frames are sent to the
0x19)"), it
Table 128
through
Table
131)
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
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