Rx Fifo Transfer Threshold Port 2 ($0X5Ba); Rx Fifo Transfer Threshold Port 3 ($0X5Bb); Datasheet - Intel IXF1104 Datasheet

Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)
Bit Name
Register Description: RX FIFO transfer threshold for port 2 in 8-byte location.
31:12 Reserved
RX FIFO Transfer
11:0
Threshold - Port 2
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)
Bit
Register Description: RX FIFO transfer threshold for port 3 in 8-byte location.
31:12
11:0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Description
Reserved
RX FIFO transfer threshold for port 2. This must be
less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP is
received. Packets received in the RX FIFO below
this threshold are treated as store and forward.
NOTE: Do not program the RX FIFO transfer
Name Description
Reserved Reserved
RX FIFO transfer threshold for port 3. This must
be less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP
RX FIFO Transfer
is received. Packets received in the RX FIFO
Threshold - Port 3
below this threshold are treated as store and
forward.
NOTE: Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
threshold below a setting of 0xBE
(1520bytes).
Type Default
0x000000BE
RO 0x00000
R/W 0x0BE
Type Default
0x000000BE
RO 0x00000
R/W 0x0BE
202