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8.3
Per Port Registers
Section 8.4
registers perform an identical function in each port.
The address vector for the IXF1104 MAC is 11 bits wide. This allows for 7 bits of port-specific
access and a 4-bit vector to address each port and all global registers. The address format is shown
in
Figure
54.
Figure 54. Register Overview Diagram
10
8.4
Register Map
Table 59
through
IXF1104 MAC memory map details. Global control and status registers are used to configure or
report on all ports, and some registers are replicated on a per-port basis.
Note: All IXF1104 MAC registers are 32 bits.
Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)
Register
"Station Address ($ Port_Index +0x00 – +0x01)" Low
"Station Address ($ Port_Index +0x00 – +0x01)" High
"Desired Duplex ($ Port_Index + 0x02)"
"FD FC Type ($ Port_Index + 0x03)"
Reserved
"Collision Distance ($ Port_Index + 0x05)"
"Collision Threshold ($ Port_Index + 0x06)"
"FC TX Timer Value ($ Port_Index + 0x07)"
"FD FC Address ($ Port_Index + 0x08 – + 0x09)"
FDFCAddressLow
"FD FC Address ($ Port_Index + 0x08 – + 0x09)"
FDFCAddressHigh
"IPG Receive Time 1 ($ Port_Index + 0x0A)"
"IPG Receive Time 2 ($ Port_Index + 0x0B)"
"IPG Transmit Time ($ Port_Index + 0x0C)"
Reserved
"Pause Threshold ($ Port_Index + 0x0E)"
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
covers all of the registers that are replicated in each port of the IXF1104 MAC. These
Port Select & Global Registers
Table 69 "Optical Module Registers ($ 0x799 - 0x79F)" on page 162
6
Per-Port Registers
1
Bit Size
Mode
Ref Page
32
R/W
163
32
R/W
163
32
R/W
163
32
R/W
163
32
R
32
R/W
164
32
R/W
164
32
R/W
164
32
R/W
164
32
R/W
164
32
R/W
165
32
R/W
165
32
R/W
165
–
RO
32
R/W
166
0
present the
Offset
0x00
0x01
0x02
0x03
–
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
–
0x0D
0x0E
156
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