Intel IXF1104 Datasheet page 45

®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 7 of 8)
Signal Name
MPHY
RERR_0
RVAL_0
RSOP_0
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Type
Designator
SPHY
RERR_0 A16
RERR_1 G17
Output
RERR_2 D20
RERR_3 H20
RVAL_0 C15
RVAL_1 B18
Output
RVAL_2 E19
RVAL_3 F22
RSOP_0 B16
RSOP_1 C18
Output
RSOP_2 E23
RSOP_3 J18
Standard Description
Receive Error.
RERR indicates that the current packet is in
error. RERR is only asserted when REOP is
asserted. Conditions that can cause RERR
to be set include FIFO overflow, CRC error,
code error, and runt or giant packets.
NOTE: RERR can only be set for these
conditions if bit 0 in the
Receive Configuration ($0x701)"
3.3 V
set to 1.
LVTTL
RERR is considered valid only when RVAL
is asserted.
32-bit Multi-PHY mode: RERR_0 covers
all 32 bits.
4 x 8 Single-PHY mode: The RERR_0:3
bits correspond to the RDAT[7:0]_n
channels.
(n = 0, 1, 2, or 3)
Receive Data Valid.
RVAL indicates the validity of the receive
data signals. RVAL is Low between
transfers and assertion of RSX. It is also
Low when the IXF1104 MAC pauses a
transfer due to an empty receive FIFO.
When a transfer is paused by holding RENB
High, RVAL holds its value unchanged,
although no new data is present on
RDAT[31:0] until the transfer resumes.
When RVAL is High, the RDAT[31:0],
3.3 V
RMOD[1:0], RSOP, REOP, and RERR
LVTTL
signals are valid. When RVAL is Low, the
RDAT[31:0], RMOD[1:0], RSOP, REOP, and
RERR signals are invalid and must be
disregarded.
The RSX signal is valid only when RVAL is
Low.
32-bit Multi-PHY mode: RVAL_0 covers all
receive bits.
4 x 8 Single-PHY mode: The RVAL_0:3
bits correspond to the per-port data and
control signals.
Receive Start of Packet.
RSOP indicates the start of a packet when
asserted with RVAL.
3.3 V
32-bit Multi-PHY mode: RSOP_0 covers
LVTTL
all 32 bits.
4 x 8 Single-PHY mode: The RSOP_0:3
bits correspond to the RDAT[7:0]_n
channels.
"SPI3
is
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005