Table of Contents
Advertisement
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 11. LED Interface Signal Descriptions
Signal Name
LED_CLK
LED_DATA
LED_LATCH
Table 12. JTAG Interface Signal Descriptions
Signal Name
TCLK
TMS
TDI
TDO
TRST_L
Table 13. System Interface Signal Descriptions
Signal Name
CLK125
SYS_RES_L
55
Ball
Type
Standard
Designator
2.5 V
K24
Output
CMOS
2.5 V
M22
Output
CMOS
2.5 V
L22
Output
CMOS
Ball
Type
Standard
Designator
3.3 V
J22
Input
LVTTL
3.3 V
H22
Input
LVTTL
3.3 V
J24
Input
LVTTL
3.3 V
H24
Output
LVTTL
3.3 V
J23
Input
LVTTL
Ball
Type
Standard
Designator
2.5 V
AD19
Input
CMOS
2.5 V
AD12
Input
CMOS
Description
LED_CLK is the clock output for the LED block.
LED_DATA is the data output for the LED block.
LED_LATCH is the latch enable for the LED block.
Description
JTAG Test Clock
Test Mode Select
Test Data Input
Test Data Output
Test Reset; reset input for JTAG test
Description
CLK125 is the input clock to PLL; 125 MHz +/-
50 ppm
SYS_RES_L is the system hard reset (active Low).
Document Number: 278757
Revision Date: 27-Oct-2005
Datasheet
Revision Number: 009
Advertisement
Table of Contents
