Tx Fifo Overflow Frame Drop Counter Ports 0 - 3 ($0X621 – 0X624); Datasheet - Intel IXF1104 Datasheet

Table 137. TX FIFO Port Reset ($0x620) (Sheet 2 of 2)
Bit Name
2 Port 2 Reset
1 Port 1 Reset
0 Port 0 Reset
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 138. TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)
Name
TX FIFO overflow
frame drop counter
on Port 0
TX FIFO overflow
frame drop counter
on Port 1
TX FIFO overflow
frame drop counter
on Port 2
TX FIFO overflow
frame drop counter
on Port 3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Description
Port 2
0 = De-assert Reset
1 = Assert Reset
Port 1
0 = De-assert Reset
1 = Assert Reset
Port 0
0 = De-assert Reset
1 = Assert Reset
Description
When TX FIFO on Port 0 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
When TX FIFO on Port 1 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
When TX FIFO on Port 2 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
When TX FIFO on Port 3 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
1
Type Default
R/W
R/W
R/W
*
Address Type Default
0x621 R 0x00000000
0x622 R 0x00000000
0x623 R 0x00000000
0x624 R 0x00000000
0
0
0
208