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Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3)
SPI3 Signals
MPHY
TERR_0
GND
GND
GND
TSOP_0
GND
GND
GND
TEOP_0
GND
GND
GND
TMOD[1:0]
TSX
TADR[1:0]
PTPA
DTPA_0:3
STPA
RDAT[31:24]
RDAT[23:16]
RDAT[15:8]
RDAT[7:0]
RFCLK
RPRTY_0
NC
NC
NC
RENB_0
VDD2
VDD2
VDD2
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball Number
SPHY
TERR_0
A8
TERR_1
K1
TERR_2
E11
TERR_3
J8
TSOP_0
C7
TSOP_1
E3
TSOP_2
C10
TSOP_3
J5
TEOP_0
A7
TEOP_1
F3
TEOP_2
E4
TEOP_3
H5
GND
D9
A6
GND
E1
TADR[1:0]
A12
A11
PTPA
B11
DTPA_0:3
D3
L1
NC
C11
F24
G24
RDAT[7:0]_3
G21
G20
E21
E22
RDAT[7:0]_2
C21
C20
F18
E18
RDAT[7:0]_1
E16
D16
F14
E14
RDAT[7:0]_0
C14
B14
RFCLK
A19
RPRTY_0
E15
RPRTY_1
G16
RPRTY_2
E20
RPRTY_3
F20
RENB_0
A13
RENB_1
A18
RENB_2
C19
RENB_3
E24
MPHY: Use TERR_0 as the TERR
signal.
SPHY: Each port has its own dedicated
TERR_n signal
MPHY: Use TSOP_0 as the TSOP
signal.
SPHY: Each port has a dedicated
TSOP_n signal.
MPHY: Use TEOP_0 as the TEOP
signal.
SPHY: Each port has a dedicated
TEOP_n signal.
TSX and TMOD[1:0] are only applicable
in MPHY mode.
Used to address port for PTPA signal.
PTPA can be used in MPHY and SPHY
modes.
DTPA is available on a per-port basis in
A9
J7
both MPHY and SPHY modes.
STPA is only applicable in MPHY mode.
G23
G22
G19
G18
D22
C22
MPHY: Consists of a single 32 bit data
B22
B20
bus.
SPHY: Separate 8-bit data bus for each
E17
F16
Ethernet port.
C17
A17
D14
C13
A15
A14,
To achieve maximum bandwidth, set
RFCLK as follows:
MPHY: 133 MHz.
SPHY: 125 MHz.
MPHY: Use RPRTY_0 as the RPRTY
signal.
SPHY: Each port has a dedicated
RPRTY_n signal.
MPHY: Use RENB_0 as the RENB
signal.
SPHY: Each port has a dedicated
RENB_n signal
Comments
60
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