Intel IXF1104 Datasheet
Intel IXF1104 Datasheet

Intel IXF1104 Datasheet

4-port gigabit ethernet media access controller
Table of Contents

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®
Intel
IXF1104 4-Port Gigabit Ethernet
Media Access Controller
®
The Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller (hereafter referred to as
the IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC
supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or
ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
The copper PHY interface supports the standard and reduced pin-count Gigabit Media
Independent Interface (GMII and RGMII) for high-port-count applications. For fiber
applications the integrated Serializer/Deserializer (SerDes) on each port supports direct
connection to optical modules to reduce PCB area requirements and system cost.

Product Features

Four Independent Ethernet MAC Ports for
Copper or Fiber Physical layer connectivity.
— IEEE 802.3 compliant
— Independent Enable/Disable of any port
Copper Mode:
— RGMII for 10/100/1000 Mbps links
— GMII for 1000 Mbps full-duplex links
— IEEE 802.3 MDIO interface
Fiber Mode:
— Integrated SerDes interface for direct
connection to 1000BASE-X optical modules
— IEEE 802.3 auto-negotiation or forced mode
— Supports SFP MSA-compatible transceivers
SPI3 interface supports data transfers up to
4 Gbps in both modes:
— 32-bit Multi-PHY mode (133 MHz)
— 4 x 8-bit Single-PHY mode (125 MHz)
IEEE 802.3-compliant Flow Control
— Loss-less up to 9.6 KB packets and 5 km links
— Jumbo frame support for 9.6 KB packets
Internal per-channel FIFOs: 32 KB Rx, 10 KB Tx
Flexible 32/16/8-bit CPU interface
Applications
Load Balancing Systems
MultiService Switches
Web Caching Appliances
Intelligent Backplane Interfaces
Edge Routers
Redundant Line Cards
Datasheet
Programmable Packet handling
— Filter broadcast, multicast, unicast, VLAN
and errored packets
— Automatically pad undersized Tx packets
— Remove CRC from Rx packets
Performance Monitoring and Diagnostics
— RMON Statistics
— CRC calculation and error detection
— Detection of length error, runt, or overly
large packets
— Counters for dropped and errored packets
— Loopback modes
— JTAG boundary scan
.18 μ CMOS process technology
— 1.8 V core, 2.5 V RGMII, GMII, OMI, and
3.3 V SPI3 and CPU
Operating Temperature Ranges:
— Copper Mode: -40°C to +85°C
— Fiber Mode:
0°C to +70°C
Package Options:
— 552-ball Ceramic BGA (standard)
— 552-ball Ceramic BGA (RoHS-compliant)
— 552-ball Plastic FC-BGA (contact your Intel
Sales Representative)
Base Station Controllers and Transceivers
Serving GPRS Support Nodes (SGSN)
Gateway GPRS Support Nodes (GGSN)
Packet Data Serving Nodes (PDSN)
DSL Access Multiplexers (DSLAM)
Cable Modem Termination Systems (CMTS)
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

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Summary of Contents for Intel IXF1104

  • Page 1: Product Features

    The Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller (hereafter referred to as the IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
  • Page 2 The IXF1104 MAC Media Access Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
  • Page 3: Table Of Contents

    Contents Introduction...20 What You Will Find in This Document ... 20 Related Documents ... 20 General Description ...21 Ball Assignments and Ball List Tables... 23 Ball Assignments ... 23 Ball List Tables ... 24 3.2.1 Balls Listed in Alphabetic Order by Signal Name ... 24 3.2.2 Balls Listed in Alphabetic Order by Ball Location ...
  • Page 4 Contents 5.1.5.1 Speed... 78 5.1.5.2 Duplex... 78 5.1.5.3 Copper Auto-Negotiation ... 78 5.1.6 Jumbo Packet Support ... 78 5.1.6.1 Rx Statistics ... 79 5.1.6.2 TX Statistics ... 79 5.1.6.3 Loss-less Flow Control... 79 5.1.7 Packet Buffer Dimensions ... 80 5.1.7.1 TX and RX FIFO Operation ...
  • Page 5 5.6.2.6 Transmit Jitter ... 106 5.6.2.7 Receive Jitter ... 106 Optical Module Interface ... 107 5.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals ... 107 5.7.2 Functional Descriptions ... 108 5.7.2.1 High-Speed Serial Interface ... 108 5.7.2.2 Low-Speed Status Signaling Interface ... 108 5.7.3...
  • Page 6 Contents Applications ... 130 Change Port Mode Initialization Sequence... 130 Disable and Enable Port Sequences ... 131 6.2.1 Disable Port Sequence ... 131 6.2.2 Enable Port Sequence... 131 Electrical Specifications ... 132 DC Specifications ... 133 7.1.1 Undershoot / Overshoot Specifications ... 135 7.1.2 RGMII Electrical Characteristics ...
  • Page 7 34 Line Side Interface Loopback Path... 127 35 SPI3 Receive Interface Timing ... 137 36 SPI3 Transmit Interface Timing ... 139 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® IXF1104 MAC Ports (8-Bit Interface) ... 90 Contents...
  • Page 8 Contents 37 RGMII Interface Timing ... 141 38 1000BASE-T Transmit Interface Timing ... 142 39 1000BASE-T Receive Interface Timing ... 143 40 SerDes Timing Diagram ... 144 41 MDC High-Speed Operation Timing ... 145 42 MDC Low-Speed Operation Timing... 145 43 MDIO Write Timing Diagram ...
  • Page 9 29 SerDes Driver TX Power Levels ...104 ® 30 Intel IXF1104 MAC-to-SFP Optical Module Interface Connections ... 107 31 LED Interface Signal Descriptions ... 116 32 Mode 0 Clock Cycle to Data Bit Relationship ... 117 33 Mode 1 Clock Cycle to Data Bit Relationship ... 118 34 LED_DATA# Decodes ...
  • Page 10 Contents 75 FC TX Timer Value ($ Port_Index + 0x07) ... 164 76 FD FC Address ($ Port_Index + 0x08 – + 0x09) ... 164 77 IPG Receive Time 1 ($ Port_Index + 0x0A) ... 165 78 IPG Receive Time 2 ($ Port_Index + 0x0B) ... 165 79 IPG Transmit Time ($ Port_Index + 0x0C) ...
  • Page 11 125 RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) ...198 126 RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)... 199 127 RX FIFO Padding and CRC Strip Enable ($0x5B3) ... 200 128 RX FIFO Transfer Threshold Port 0 ($0x5B8) ... 201 129 RX FIFO Transfer Threshold Port 1 ($0x5B9) ...
  • Page 12: Datasheet

    Contents Revision History Page # Description Modified Section 45, “RGMII Power” Added bullet to supports random single-byte reads and does not guarantee coherency when reading two-byte registers. Replaced Modified Modified Modified Modified Added Section 9.3.3, “Top Label Marking Modifed Section 10.0, “Product Ordering Page # Description Added 552-ball Ceramic Ball Grid Array (CBGA) compliant with RoHS and Product Ordering...
  • Page 13: 0X00200000

    Page # Description Modified register from “0x0001A0” to “0x000001A0” and changed default value for bit 6 (Half Duplex) from 1 to 0]. Modified descriptions of register” and register default value]. Modified of register” and register default value]. Modified descriptions of register” and register default value]. Modified descriptions of register”...
  • Page 14 Updated Figure 4 “Interface Signals” [modified SPI3 interface signals and added MPHY and SPHY categories; modified signal names]. Broke old Table 1, “IXF1104 Signal Descriptions” into the following: Table 3 “SPI3 Interface Signal Descriptions” on page 39 through Table 14 “Power Supply Signal Descriptions”...
  • Page 15 Modified Section 5.1.7.1.2, “RX FIFO” [changed 10 KB to 9.6 KB; added text to last paragraph]. Rewrote/replaced Section 5.2, “SPI3 Interface”. Edited signal names in Figure 13 “MPHY 32-Bit Interface”. Edited signal names in Figure 16 “SPHY Connection for Two Intel Interface)”. Added new Section 5.2.2.9, “SPI3 Flow Control”.
  • Page 16: Datasheet

    44 “MDIO Read Timing Diagram”, and Table 52 “MDIO Timing Parameters”. Revision Number: 007 Revision Date: March 24, 2004 (Sheet 3 of 5) ® IXF1104 MAC-to-SFP Optical Module Interface Connections” [edited C Write Operation” [edited portions of text]. C Clock]. C Clock” [from GBIC Clock to I C Clock].
  • Page 17 Page # Description Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”, Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics Registers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”, Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”, Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)”, Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)”, Table 66 “MDIO Registers ($ 0x680 - 0x683)”, Table 67 “SPI3 Registers ($ 0x700 - 0x716)”, Table 68 “SerDes...
  • Page 18: Datasheet

    Revision Date: March 24, 2004 (Sheet 5 of 5) Revision Number: 006 Revision Date: August 21, 2003 (Sheet 1 of 2) ® IXF1104 Signal Descriptions” ® IXF1104-to-Optical Module Interface Connections” Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005...
  • Page 19 Revision Number: 009 Revision Date: 27-Oct-2005 Revision Number: 006 Revision Date: August 21, 2003 (Sheet 2 of 2) ® IXF1104 Example Package Marking”. Revision 005 Revision Date: April 30, 2003 Revisions 001 through 004 Revision Date: April 2001 – December 2002 Contents...
  • Page 20: Introduction

    • Section 4.0, “Ball Assignments and Signal Descriptions” on page 37 IXF1104 ball grid diagram with two ball list tables (by signal name and ball location) • Section 5.0, “Functional Descriptions” on page 66 operation of the IXF1104 including general features, and interface types and descriptions.
  • Page 21: General Description

    IXF1104 4-Port Gigabit Ethernet Media Access Controller General Description The IXF1104 MAC provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full- duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network processor is supported through a System Packet Interface Phase 3 (SPI3) media interface.
  • Page 22: Internal Architecture

    IXF1104 MAC internal architecture. Figure 2. Internal Architecture SPI3 Interface Clock Control Block Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller CPU Interface RMON Statistics Packet Buffer Packet Buffer Packet Buffer Packet...
  • Page 23: Ball Assignments And Ball List Tables

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Assignments and Ball List Tables Ball Assignments Figure Table 1 “Ball List in Alphanumeric Order by Signal Name” on page “Ball List in Alphanumeric Order by Ball Location” on page 30 assignments.
  • Page 24: Ball List Tables

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball List Tables 3.2.1 Balls Listed in Alphabetic Order by Signal Name Table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name. The following table notes relate to 1.
  • Page 25 Signal Name Location Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Ball Signal Name Location AD21 C_CLK C_DATA_0 C_DATA_1 C_DATA_2 C_DATA_3 LED_CLK LED_DATA LED_LATCH MDIO MOD_DEF_INT AA12 AA13...
  • Page 26 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Pad PTPA RDAT_0 RDAT_1 RDAT_2 RDAT_3 RDAT_4 RDAT_5...
  • Page 27 TDAT15 TDAT16 TDAT17 TDAT18 TDAT19 TDAT20 TDAT21 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Ball Signal Name Location AC11 TDAT22 TDAT23 TDAT24 TDAT25 AA11 TDAT26 TDAT27 TDAT28...
  • Page 28 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name TXD4_1 TXD4_2 TXD4_3 TXD5_0 TXD5_1 TXD5_2 TXD5_3 TXD6_0 TXD6_1 TXD6_2 TXD6_3 TXD7_0 TXD7_1 TXD7_2 TXD7_3 TXPAUSE_ADD0 TXPAUSE_ADD1 TXPAUSE_ADD2 TXPAUSEFR UPX_ADD0 UPX_ADD1 UPX_ADD2 UPX_ADD3 UPX_ADD4 UPX_ADD5 UPX_ADD6 UPX_ADD7 UPX_ADD8 UPX_ADD9...
  • Page 29 VDD4 VDD4 VDD4 VDD4 VDD5 VDD5 VDD5 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Ball Signal Name Location VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5...
  • Page 30: Balls Listed In Alphabetic Order By Ball Location

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 3.2.2 Balls Listed in Alphabetic Order by Ball Location Table 2 shows the ball locations and signal names arranged in order by ball location. Table 2. Ball List in Alphanumeric Order by Ball Location...
  • Page 31 TDAT22 VDD2 VDD3 RDAT_7 RDAT_12 VDD3 RDAT_15 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Signal Name Location RPRTY_3 RVAL_3 RDAT_31 TDAT9 TDAT10 TPRTY_1 TDAT24 TDAT25 TDAT26 TDAT27...
  • Page 32 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Signal Name Location TERR_1 UPX_DATA1 UPX_DATA7 UPX_DATA17 UPX_DATA21 UPX_DATA23 UPX_DATA25 LED_CLK DTPA_1 UPX_DATA0 UPX_DATA2 UPX_DATA4 UPX_DATA9 UPX_DATA10 UPX_DATA12 Ball Signal Name Location UPX_DATA31 LED_LATCH C_CLK C_DATA_0 UPX_RDY_L VDD2 UPX_DATA3 UPX_DATA6...
  • Page 33 RX_N_0 RX_N_2 UPX_ADD4 UPX_BADD0 UPX_ADD10 UPX_WR_L UPX_WIDTH1 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Signal Name Location VDD5 VDD4 RXD4_3 RXD5_3 RXD6_3 RXD7_3 TXPAUSEFR AVDD1P8_2 RX_P_2 UPX_ADD5...
  • Page 34 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Signal Name Location VDD5 VDD4 TXD7_3 TX_P_2 VDD4 RXD3_3 RXD7_2 RXD4_2 TXD0_0 TXD1_0 TXD2_0 TXD7_0 RXD5_0 RXD4_0 RXD3_0 TX_EN_1 RXD0_1 RXD7_1 RXD1_1 RX_ER_1 TX_P_0 TX_N_0 TXD5_3 TX_N_2 RXD0_3 RXD1_3 RXD2_3...
  • Page 35 COL_2 AD16 TXD4_2 AD17 TX_ER_2 AD18 TX_N_3 AD19 CLK125 AD20 AVDD2P5_1 AD21 AD22 No Ball AD23 No Ball AD24 No Ball Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller...
  • Page 36 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005...
  • Page 37: Ball Assignments And Signal Descriptions

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Assignments and Signal Descriptions Naming Conventions 4.1.1 Signal Name Conventions Signal names begin with a Signal Mnemonic, and can also contain one or more of the following designations: a differential pair designation, a serial designation, a port designation (RGMII interface), and an active low designation.
  • Page 38: Interface Signal Groups

    Interface Signal Groups This section describes the IXF1104 MAC signals in groups according to the associated interface or function. Figure 4 shows the various interfaces available on the IXF1104 MAC. Figure 4. Interface Signals SPHY TDAT[7:0]_0:3 TENB_0:3 TERR _0:3 TPR TY_0:3...
  • Page 39: Signal Description Tables

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Description Tables The I/O signals, power supplies, or ground returns associated with each IXF1104 MAC connection ball are described in Table 3 Table 3. SPI3 Interface Signal Descriptions (Sheet 1 of 8)
  • Page 40 TEOP_2 TEOP_3 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard Description Designator Transmit Parity. TPRTY indicates odd parity for the TDAT bus. TPRTY is valid only when a channel asserts either TENB or TSX.
  • Page 41 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 3 of 8) Signal Name MPHY SPHY TMOD1 TMOD0 TADR1 TADR1 TADR0 TADR0 Ball Type Standard Description Designator TMOD[1:0] Transmit Word Modulo. 32-bit Multi-PHY mode: TMOD[1:0] indicates the valid data bytes of TDAT[31:0].
  • Page 42 DTPA_3 DTPA_3 STPA Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard Description Designator DTPA_0:3 Direct Transmit Packet Available. A direct status indication for transmit FIFOs of ports 0:3.
  • Page 43 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 5 of 8) Signal Name MPHY SPHY PTPA PTPA RDAT31 RDAT7_3 RDAT30 RDAT6_3 RDAT29 RDAT5_3 RDAT28 RDAT4_3 RDAT27 RDAT3_3 RDAT26 RDAT2_3 RDAT25 RDAT1_3 RDAT24...
  • Page 44 RENB_2 RENB_3 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard Description Designator Receive Data Bus. RDAT carries payload data and in-band addresses from the IXF1104 MAC.
  • Page 45 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 7 of 8) Signal Name MPHY SPHY RERR_0 RERR_0 RERR_1 RERR_2 RERR_3 RVAL_0 RVAL_0 RVAL_1 RVAL_2 RVAL_3 RSOP_0 RSOP_0 RSOP_1 RSOP_2 RSOP_3 Ball Type...
  • Page 46 RMOD1 RMOD0 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard Description Designator Receive End of Packet. REOP indicates the end of a packet when asserted with RVAL.
  • Page 47: Serdes Interface Signal Descriptions

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 4. SerDes Interface Signal Descriptions Signal Name Ball Designator TX_P_0 TX_P_1 AD13 TX_P_2 TX_P_3 AC18 TX_N_0 TX_N_1 AD14 TX_N_2 TX_N_3 AD18 RX_P_0 RX_P_1 RX_P_2 RX_P_3 RX_N_0 RX_N_1 RX_N_2 RX_N_3 1. Internally terminated differentially with 100 Ω.
  • Page 48: Gmii Interface Signal Descriptions

    NOTE: Refer to the RGMII interface for shared data and clock signals. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Designator Type Standard 2.5 V Output CMOS AA18...
  • Page 49 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 5. GMII Interface Signal Descriptions (Sheet 2 of 2) Signal Name RXD7_0 RXD6_0 RXD5_0 RXD4_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 RXD7_1 RXD6_1 RXD5_1 RXD4_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 RXD7_2 RXD6_2 RXD5_2...
  • Page 50: Rgmii Interface Signal Descriptions

    AA24 RXC_3 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Type Standard Description Source Synchronous Transmit Clock. 2.5 V Output This clock is supplied synchronous to the transmit CMOS data bus in either RGMII or GMII mode.
  • Page 51: Cpu Interface Signal Descriptions

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 6. RGMII Interface Signal Descriptions (Sheet 2 of 2) Ball Signal Name Designator RD3_0 RD2_0 RD1_0 RD0_0 RD3_1 RD2_1 RD1_1 RD0_1 RD3_2 RD2_2 RD1_2 RD0_2 RD3_3 RD2_3 RD1_3 RD0_3 RX_CTL_0...
  • Page 52 UPX_RD_L UPX_RDY_L UPX_WIDTH1 UPX_WIDTH0 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard Description Data bus. 32-bit mode: Uses [31:0] Input/ 3.3 V LVTTL Output 16-bit mode: Uses [15:0]...
  • Page 53: Transmit Pause Control Interface Signal Descriptions

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 8. Transmit Pause Control Interface Signal Descriptions Signal Name Designator TXPAUSEADD2 TXPAUSEADD1 TXPAUSEADD0 TXPAUSEFR Table 9. Optical Module Interface Signal Descriptions (Sheet 1 of 2) Signal Name Designator TX_DISABLE_0 TX_DISABLE_1...
  • Page 54: Mdio Interface Signal Descriptions

    Designator MDIO Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard Description Transmitter Fault Interrupt. TX_FAULT_INT is an open drain interrupt output that signals a TX_FAULT condition.
  • Page 55: Led Interface Signal Descriptions

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 11. LED Interface Signal Descriptions Signal Name Designator LED_CLK LED_DATA LED_LATCH Table 12. JTAG Interface Signal Descriptions Signal Name Designator TCLK TRST_L Table 13. System Interface Signal Descriptions Signal Name...
  • Page 56: Power Supply Signal Descriptions

    AVDD2P5_2 VDD2 VDD3 VDD4 AC21 VDD5 AC12 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Designator Type Standard Input AA12 AA13 AA17 AB12 AC10 AC15 AC19 AD21 Input 1.8 V...
  • Page 57: Ball Usage Summary

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Usage Summary Table 15. Ball Usage Summary Type Inputs Outputs Bi-directional Total Signals Power Ground No Connects Total Quantity Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005...
  • Page 58: Multiplexed Ball Connections

    2. An open drain I/O, external 4.7 k Ω pull-up resistor is required. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Fiber Mode Unused Port Optical Module/ SerDes Signal TX_DISABLE_0:3 MOD_DEF_0:3...
  • Page 59: Spi3 Mphy/Sphy Ball Connections

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 16. Line Side Interface Multiplexed Balls (Sheet 2 of 2) Copper Mode GMII Signal RGMII Signal MDIO MDIO 1. An external pull-up resistor is required with most optical modules. 2. An open drain I/O, external 4.7 k Ω pull-up resistor is required.
  • Page 60 VDD2 RENB_3 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Number SPHY A14, Comments MPHY: Use TERR_0 as the TERR signal. SPHY: Each port has its own dedicated...
  • Page 61: Ball State During Reset

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 17. SPI3 MPHY/SPHY Interface (Sheet 3 of 3) SPI3 Signals MPHY SPHY RERR_0 RERR_0 RERR_1 RERR_2 RERR_3 RVAL_0 RVAL_0 RVAL_1 RVAL_2 RVAL_3 RSOP_0 RSOP_0 RSOP_1 RSOP_2 RSOP_3 REOP_0 REOP_0 REOP_1...
  • Page 62 C_CLK C_DATA_0:3 NOTE: Z = High impedance. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Reset State Comment – High Z Bi-directional – High Z Bi-directional Open-drain output, requires an external pull-up –...
  • Page 63: Power Supply Sequencing

    IXF1104 MAC operation. The sequence described in and analog supplies. Caution: Failure to follow the sequence described in this section might damage the IXF1104 MAC. 4.7.1 Power-Up Sequence Ensure that the 1.8 V analog and digital supplies are applied and stable prior to application of the 2.5 V analog and digital supplies.
  • Page 64: Pull-Up/Pull-Down Ball Guidelines

    NOTE: To avoid damage to the IXF1104 MAC, the TXAV25 supply must not exceed the VDD supply by more than 2 V at any time during the power-up or power-down sequence.
  • Page 65: Analog Power Supply Filter Network

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 6. Analog Power Supply Filter Network Table 21. Analog Power Balls Signal Name AVDD1P8_1 AVDD2P5_1 AVDD1P8_2 AVDD2P5_2 Ball Comments Designator Need to provide a filter (see R: AVDD1P8_1 and AVDD2P5_1 = 5.6 Ω resistor.
  • Page 66: Functional Descriptions

    Support for non-standard packet sizes up to 10 KB including loss-less flow control Note: The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode. The IXF1104 MAC is fully integrated, designed for use with Ethernet 802.3 frame types, and compliant to all of the IEEE 802.3 MAC requirements.
  • Page 67: Features For Fiber And Copper Mode

    This feature is enabled when bit 0 of the Any frame received in this mode that does not match the Station Address (MAC address) is marked by the IXF1104 MAC to be dropped. The frame is dropped if the appropriate bit in the Errored Frame Drop Enable ($0x59F)"...
  • Page 68 This feature is enabled when bit 1 of the Any frame received in this mode that does not match the Port Multicast Address (reserved multicast address recognized by IXF1104 MAC) is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the...
  • Page 69: Crc Error Detection

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller When the CRC Error Pass Filter bit = 0 takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0.
  • Page 70: Flow Control (Full-Duplex Operation)

    When the RX FIFO reaches a watermark (either exceeding a High or dropping below a Low after exceeding a High), the IXF1104 control sublayer signals an internal state machine to transmit a PAUSE frame. The FIFOs automatically generate PAUSE frames (also called control frames) to initiate the following: •...
  • Page 71: Packet Buffering Fifo

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 7. Packet Buffering FIFO SPI3 Interface High Watermark MAC Transfer Threshold Low Watermark High Watermark Low Watermark TXPAUSEFR (External Strobe) 5.1.2.1.1 Pause Frame Format PAUSE frames are MAC control frames that are padded to the minimum size (64 bytes).
  • Page 72: Pause Frame Format

    Pause Length that the MAC transmits another Pause frame to maintain the link partner in the pause state. The transmitted Pause Length in the IXF1104 MAC is set by the Port_Index + 0x07)” on page The IXF1104 PAUSE frame transmission interval is set by the 0x0E)”...
  • Page 73 31B) or has a Destinations Address matching the address programmed in the ($ Port_Index +0x00 – 2. If the PAUSE frame is valid, the transmit side of the IXF1104 pauses for the required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.
  • Page 74: Transmit Pause Control Interface

    Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Operation of TX Pause Control Interface Transmits a PAUSE frame on every port with a pause_time = ZERO (XON) (Cancels all previous pause commands). Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed in the port 0 “FC TX Timer Value ($ Port_Index + 0x07)"...
  • Page 75: Mixed-Mode Operation

    5.1.3 Mixed-Mode Operation The IXF1104 MAC gives the user the option of configuring each port for 10/100 Mbps half-duplex copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-duplex fiber operation. This gives the IXF1104 MAC the ability to support both copper and fiber operation line-side interfaces operating at the same time within a single device.
  • Page 76: Fiber Mode

    IXF1104 MAC. 5.1.4 Fiber Mode When the IXF1104 MAC is configured for fiber mode, the TX Data path from the MAC is an internal 10-bit interface as described in the IEEE 802.3z specification. It is connected directly to an internal SerDes block for serialization/deserialization and transmission/reception on the fiber medium to and from the link partner.
  • Page 77: Fiber Auto-Negotiation

    5.1.5 Copper Mode In copper mode, the IXF1104 MAC transmits data on the egress path of the RGMII or GMII interface, depending on the port configuration defined by the user. The copper MAC receives data on the ingress path of the RGMII or GMII interface, depending on the port configuration defined 58).
  • Page 78: Speed

    MAC speed setting must be programmed by the system software to match the speed of the attached PHY for proper IXF1104 MAC operation. Note: When the IXF1104 MAC is configured to use the GMII interface, the only mode of operation that is supported is 1000 Mbps full-duplex.
  • Page 79: Rx Statistics

    9.6 k bytes. If this condition is met, the IXF1104 MAC has sufficient memory resources allocated to each MAC port to ensure that, if both the IXF1104 MAC and link partner are required to send Pause packets simultaneously during jumbo packet transfers across a medium of five kilometers of fiber, no packet data should be lost due to FIFO overflows.
  • Page 80: Packet Buffer Dimensions

    5.1.7.1.2 RX FIFO The IXF1104 MAC RX FIFOs are provisioned so that each port has its own 32 KB of memory space. This is enough memory to ensure that there is never an over-run on any channel while transferring normal Ethernet frame size data.
  • Page 81: Rmon Additional Statistics

    The 0 - 3 ($0x594 – 0x597)" the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any IXF1104 MAC programmable packet filtering is enabled, the Ports 0 - 3 ($0x5A2 - 0x5A5)"...
  • Page 82: Conventions

    The 0 - 3 ($0x594 – 0x597)" the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any IXF1104 MAC programmable packet filtering is enabled, the Ports 0 - 3 ($0x5A2 - 0x5A5)"...
  • Page 83: Advantages

    3.2 Gbps when operating at a frequency of 104 MHz. The IXF1104 MAC defines operation for the transfer of data at data rates of up to 4.256 Gbps when operating at a maximum frequency of 133 MHz in MPHY mode and 125 MHz in SPHY Mode.
  • Page 84: Mphy Operation

    SPI3 RX Round Robin Data Transmission The IXF1104 MAC uses a round-robin protocol to service each of the 4 ports dependent upon the enable status of the port and if there is data available to be taken from the RX FIFO. The round robin order goes from port 0, port 1, port 2, port 3, and back to port 0.
  • Page 85: Transmit Timing

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 5.2.2.1 Transmit Timing In MPHY mode a packet transmission starts with the TSX signal indicating port address information is on the data bus. The next clock cycle TENB and TSOP indicate present data on the bus is the first word in the packet and all subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted.
  • Page 86: Mphy Receive Logical Timing

    TADR[1:0] RFCLK RDAT[31:0] RMOD[1:0] RPRTY Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 4- 7 1- 3 48- 51 52- 55 SPI3 Bus IXF1104 MPHY Mode TFCLK TENB TENB_0...
  • Page 87: Clock Rates

    To allow all four IXF1104 MAC ports to operate at 1 Gbps, the IXF1104 MAC is designed to allow this interface to be overclocked. This allows operation for data transfer at data rates of up to 4.256 Gbps when operating at an overclocked frequency of 133 MHz.
  • Page 88: Sphy Logical Timing

    RFCLK following the assertion of RENB. When REOP is asserted RMOD indicates the number of valid bytes in the last transfer. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Section 7.2, “SPI3 AC Timing Specifications” B3249-02...
  • Page 89: Sphy Receive Logical Timing

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 15. SPHY Receive Logical Timing Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005...
  • Page 90: Sphy Connection For Two Intel ® Ixf1104 Mac Ports (8-Bit Interface)

    The IXF1104 MAC allows this interface to be overclocked so that all four IXF1104 MAC ports can operate at 1 Gbps. This allows data transfer at data rates of up to 4.0 Gbps when operating at an overclocked frequency of 125 MHz.
  • Page 91: Spi3 Flow Control

    RENB can be asserted High by the Network Processor at any time if it is unable to accept any more data. When the RENB is sampled High by the IXF1104 MAC, a read of the RX FIFO is not performed, and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals remain unchanged on the following rising edge of RFCLK.
  • Page 92: Datasheet

    The port reported by STPA is updated on the rising edge of TFCLK after TSX is sampled as asserted. STPA is updated on the rising edge of TFCLK. Note: STPA is only used when the IXF1104 MAC is configured for MPHY mode of operation. PTPA: PTPA provides status of the TX FIFO based on the port selected by the TADR[1:0] address bus.
  • Page 93: Pre-Pending Function

    This results in a standard 1518-byte Ethernet packet received by the IXF1104 MAC being forwarded to the higher-layer device as a 380-long-word packet. The upper-layer device is responsible for stripping the additional two bytes.
  • Page 94: Gmii Signal Multiplexing

    Figure 38 “1000BASE-T Transmit Interface Timing” on page Receive Interface Timing” on page Parameters” on page 143 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller TXC_3:0 TXC_3:0 TXD[7:0]_0 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_2...
  • Page 95: Gmii Interface Signal Definitions

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 26. GMII Interface Signal Definitions IXF1104 MAC GMII Standard Signal TXC_0 TXC_1 TXC_2 TXC_3 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TX_EN_0 TX_EN_1 TX_EN_2 TX_EN_3 TX_ER_0 TX_ER_1 TX_ER_2 TX_ER_3 RXC_0 RXC_1 RXC_2 RXC_3...
  • Page 96: Reduced Gigabit Media Independent Interface (Rgmii)

    Reduced Gigabit Media Independent Interface (RGMII) The IXF1104 MAC supports the RGMII interface standard as defined in the RGMII Version 1.2 specification. The RGMII interface is an alternative to the IEEE 802.3u MII interface. The RGMII interface is intended as an alternative to the IEEE 802.3u MII and the IEEE 802.3z GMII.
  • Page 97: Timing Specifics

    Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 5.4.2 Timing Specifics The IXF1104 MAC RGMII complies with RGMII Rev1.2a requirements. timing specifics. 5.4.3 TX_ER and RX_ER Coding To reduce interface power, the transmit error condition (TX_ER) and the receive error condition...
  • Page 98: Tx_Ctl Behavior

    RX_CTL_0:3 RXC_0:3 (at PHY) RD[3:0]_0:3 RX_CTL_0:3 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Valid Frame TD[3:0] TD[7:4] TX_EN=True TX_ER=False End-of-Frame Frame with Error TD[3:0] TD[7:4] TX_EN=True TX_ER=False End-of-Frame...
  • Page 99: In-Band Status

    The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows the IXF1104 MAC to monitor and control each of the PHY devices that are connected to the four ports of IXF1104 MAC when those ports are in copper mode.
  • Page 100: Mdio Address

    5.5.4 MDC Generation The MDC clock is used for the MDIO/MDC interface. The frequency of the MDC clock is selectable by setting bit 0, MDC Speed, in an IXF1104 MAC configuration register (see “MDIO Control ($0x683)” on page 5.5.4.1 MDC High-Frequency Operation The high-frequency MDC is 18 MHz, derived from the 125-MHz system clock by dividing the frequency by 7.
  • Page 101: Management Frames

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Refer to Figure 42 “MDC Low-Speed Operation Timing” on page 145 timing diagram. 5.5.5 Management Frames The Management Interface serializes the external register access information into the format specified by IEEE 802.3, Section 22.2.4.5 (see Figure 21.
  • Page 102: Mdi State

    Cnt = 16 And Go = 1 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Idle Go = 1 Cnt > 32 Cnt < 32 Preamble Cnt = 32 Cnt >...
  • Page 103: Autoscan Operation

    The“Autoscan PHY Address Enable ($0x682)" occupied for each IXF1104 MAC port. The least significant bit (LSB) that is set in the register is Port 0, the next significant bit that is set is assumed to be port 1, and so on. If more than four bits are set, the bits beyond the fourth bit are ignored.
  • Page 104: Transmitter Operational Overview

    5.6.2.1 Transmitter Operational Overview The transmit section of the IXF1104 MAC has to serialize the Ten Bit Interface (TBI) data from the IXF1104 MAC MAC section and outputs this data at 1.25 GHz differential signal levels. The 1.25 GHz differential SerDes signals are compliant with the Small Form Factor Pluggable (SFP) Multi-Source Agreement (MSA).
  • Page 105: Receiver Operational Overview

    5.6.2.4 Selective Power-Down The IXF1104 MAC offers the ability to selectively power-down any of the SerDes TX or RX ports that are not being used. This is done via 5.6.2.5 Receiver Jitter Tolerance The SerDes receiver architecture is designed to track frequency mismatch, recover phase, and is tolerant of low-frequency data jitter.
  • Page 106: Transmit Jitter

    A random component attributed to random thermal noise effects. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Sinusoidal Jitter Mask 375 Hz 16 ui 22.5836 kHz 8.5 ui 1.9195 MHz 0.1 ui Frequency B0745-02...
  • Page 107: Optical Module Interface

    IXF1104 4-Port Gigabit Ethernet Media Access Controller Optical Module Interface This section describes the connection of the IXF1104 MAC ports to an Optical Module Interface and details the minimal connections that are supported for correct operation. The registers used for write control and read status information are documented.
  • Page 108: Functional Descriptions

    RX_LOS_INT 5.7.2.2.1 MOD_DEF_0:3 MOD_DEF_0:3 are direct inputs to the IXF1104 MAC and are pulled to a logic Low level during normal operation, indicating that a module is present for each channel respectively. If a module is not present, a logic High is received, which is achieved by an external pull-up resistor at the IXF1104 MAC device pad.
  • Page 109: Datasheet

    If the optical module transmitter is disabled, this signal is switched to a logic High level. On the IXF1104 MAC, these outputs are open drain types and pulled up by the 4.7 k to 10 k pull-up resistor at the Optical Module Interface. Each of these signals is controlled through bits 3:0 respectively of the 5.7.2.2.5...
  • Page 110: I²C Module Configuration Interface

    The IXF1104 MAC I SFP. The specific interface in the IXF1104 MAC supports only a subset of the full I²C interface, and only the features required to support the Optical Module Interfaces are implemented. This leads to the following support features.
  • Page 111: I 2 C Write Operation

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 1. Initialize the Control register by setting the following values: a. Enable the I b. Initiate the I c. Select the port by using bits [17:16]. d. Select the Read mode of operation by setting bit [15] to 0x1.
  • Page 112: I²C Protocol Specifics

    The Serial Clock Line (I synchronous with this clock and is driven off the rising edge by the IXF1104 MAC and off the falling edge by the optical module. The IXF1104 MAC has only one I of the optical modules.
  • Page 113: Port Protocol Operation

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 5.7.3.5 Port Protocol Operation 5.7.3.6 Clock and Data Transitions The I C_DATA is normally pulled High with an extra device. Data on the I only during the I C_CLK Low time periods (see periods indicate a start or stop condition.
  • Page 114: Acknowledge Timing

    Low, which signals a Write operation. The optical module acknowledges receipt of the device address word. The IXF1104 MAC sends the data word address, which is again acknowledged by the optical module. The IXF1104 MAC generates another start condition. This completes the “dummy”...
  • Page 115: Led Interface

    The IXF1104 MAC initiates a current address read by sending a device address with the Read/ Write bit set High. The optical module acknowledges the device address and serially clocks out the data word. The IXF1104 MAC does not respond with a zero but generates a stop condition (see Figure 28).
  • Page 116: Led Interface Signal Description

    5.8.2 LED Interface Signal Description The IXF1104 MAC LED interface consists of three output signal signals that are 2.5 V CMOS level pads. Table 31 Table 31. LED Interface Signal Descriptions Pin Name Pin # LED_CLK LED_DATA LED_LATCH 5.8.3 Mode 0: Detailed Operation Note: Please refer to the SGS Thompson* M5450 datasheet for device-operation information.
  • Page 117: Mode 1: Detailed Operation

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 32. Mode 0 Clock Cycle to Data Bit Relationship LED_CLK Cycle START BIT PAD BITS 4:15 LED DATA 1-12 36:38 PAD BITS When implemented on the board with the M5450 device, the LED DATA bit 1 appears on Output bit 3 of the M5450 and the LED DATA bit 2 appears on Output bit 4, etc.
  • Page 118: Power-On, Reset, Initialization

    The LED interface is disabled at power-on or reset. The system software controller must enable the LED interface. The internal state machines and output signals are held in reset until the full Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller device configuration is completed. This...
  • Page 119: Led Signaling Behavior

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Note: The data decode of the LED bits is independent of the Physical mode selection. Table 34. LED_DATA# Decodes LED_DATA# MAC Port # 5.8.6.1 LED Signaling Behavior Operation in each mode for the decoded LED data in 5.8.6.1.1...
  • Page 120: Cpu Interface

    {0, 1, 2} is similarly captured in internal write holding registers and the complete 32-bit write is committed when byte[3] is written to the IXF1104 MAC. When writing in 16-bit mode, bytes [1:0] are captured, and the double-word is committed when bytes [3:2] are written. The complete address for write is ignored (except for the write which causes the commit operation).
  • Page 121: Functional Description

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 5.9.1 Functional Description 5.9.1.1 Read Access Read access involves the following: • Detect assertion of asynchronous Read control signal and latch address • Generate internal Read strobe • Drive valid data onto processor bus •...
  • Page 122: Cpu Timing Parameters

    The Endian of the CPU interface may be changed to allow connection of various CPUs to the ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller. The Endian selection is determined by setting the Endian bit in the The following describes Endianness control: •...
  • Page 123: Tap Interface (Jtag)

    Asynchronous reset is achieved by pulsing or holding TRST_L Low. Synchronous reset is achieved by clocking TCLK with five clock pulses while TMS is held or floats High. This ensures that the boundary scan cells do not block the pin to core connections in the IXF1104 MAC. Little Endian...
  • Page 124: Instruction Register And Supported Instructions

    EXTEST SAMPLE IDCODE HIGHZ CLAMP Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Code Description 1111 1-bit Bypass 0000 External Test 0001 Sample Boundary 0110 ID Code Inspection 0101...
  • Page 125: Id Register

    5.10.5 Bypass Register The Bypass register is a 1-bit register that bypasses the IXF1104 MAC to reduce the JTAG chain length when accessing other devices on the chain besides the IXF1104 MAC. The BYPASS, HIGHZ, and CLAMP instructions connect this register between TDI and TDO.
  • Page 126: Line Side Interface Loopback

    To provide a diagnostic loopback feature on the line-side interfaces, the IXF1104 MAC can be configured to loop back any data received by the IXF1104 MAC through one of the line interfaces back to the corresponding transmit line interface. This is done by using the data path shown in Figure 34.
  • Page 127: Clocks

    SPI3 Interface Block When the IXF1104 MAC is configured in this loopback mode, all of the MAC functions and features are available, including flow control and pause-packet generation. To configure the IXF1104 MAC to use the line-side loopback mode, the FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)"...
  • Page 128: Clk125

    125 MHz for 1000 Mbps, 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps 5.12.4 MDC Clock The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. The IXF1104 MAC meets the following specifications for this clock: •...
  • Page 129: Jtag Clock

    2.5 V CMOS drive • Maximum clock frequency of 100 KHz 5.12.7 LED Clock The IXF1104 MAC supports a serial LED data stream and meets the following specifications for this clock: • 2.5 V CMOS drive • Maximum frequency of 720 Hz •...
  • Page 130: Applications

    Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller ($0x620)”. “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” “Interface Mode ($0x501)” “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)”...
  • Page 131: Disable And Enable Port Sequences

    Intel recommends the following sequences to disable and enable individual ports, and for dropped links. When a link is dropped, Intel recommends the port be completely reset and flushed to remove packet fragments that may interfere with the auto-negotiation process on link recovery.
  • Page 132: Electrical Specifications

    Table 39 through Table 58 “LED Interface AC Timing Parameters” on page 154 “SPI3 Receive Interface Timing” on page 137 page 154 represent the target specifications of the following IXF1104 MAC interfaces: — SPI3 — JTAG — MDIO — Pause Control —...
  • Page 133: Dc Specifications

    1000 Mbps mode Power consumption RGMII Operation Transmitting and receiving in 1000 Mbps mode DC Specifications The IXF1104 MAC supports the following I/O buffer types: • 2.5 V CMOS • 3.3 V LVTTL • SerDes Symbol 1.65 –...
  • Page 134: Serdes Transmit Characteristics

    The related driver characteristics are described in this section. Caution: IXF1104 MAC input signals are not 5 V tolerant. Devices driving the IXF1104 MAC must provide 3.3 V signal levels or use level-shifting buffers to provide 3.3 V-compatible levels. Otherwise, damage to the IXF1104 MAC will occur.
  • Page 135: Undershoot / Overshoot Specifications

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 42. SerDes Transmit Characteristics (Sheet 2 of 2) Parameter Receiver common mode voltage range Receiver termination impedance Signal detect level 1. Refer to Section 5.6.2.2, “Transmitter Programmable Driver-Power Levels” on page Table 43.
  • Page 136: Rgmii Power

    Input High Current Input Low Current Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Conditions = -1.0 A; V = 1.0 A; V > V < V = 2.5V = 0.4V...
  • Page 137: Spi3 Ac Timing Specifications

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller SPI3 AC Timing Specifications 7.2.1 Receive Interface Timing Figure 35 Table 46 Figure 35. SPI3 Receive Interface Timing RFCLK RENB RDAT[31:0] RPRY RMOD RSOP REOP RERR RVAL illustrate and provide SPI3 receive interface timing information.
  • Page 138: Spi3 Receive Interface Signal Parameters

    4. Maximum propagation delays are measured with a 30 pF load when operating OIF-SPI3 standard 104 MHz. Over-clocked rates of 125 MHz or higher are measured using a load of 20 pF. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Parameter Units – –...
  • Page 139: Transmit Interface Timing

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.2.2 Transmit Interface Timing Figure 36 Table 47 Figure 36. SPI3 Transmit Interface Timing TFCLK TENB TDAT[31:0] TPRTY TMOD[1:0] TSOP TEOP TERR TADR DTPA STPA PTPA illustrate and provide SPI3 transmit interface timing information.
  • Page 140: Spi3 Transmit Interface Signal Parameters

    3. Output propagation delay time is the time in nanoseconds from the 1.4 V point of the reference signal to the 1.4 V point of the output. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Parameter Units – – – – –...
  • Page 141: Rgmii Ac Timing Specification

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller RGMII AC Timing Specification Figure 37 Table 48 Figure 37. RGMII Interface Timing (at Transmitter) TD[3:0] TX_CTL[n] (at Receiver) (at Transmitter) RD[3:0] RX_CTL (at Receiver) Table 48. RGMII Interface Timing Parameters...
  • Page 142: Gmii Ac Timing Specification

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 49 Table 50 provide GMII AC timing specifications. Parameter C and are for design aid only; not guaranteed and not subject to production or 1 ns.
  • Page 143: 1000Base-T Receive Interface

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.4.1.2 1000BASE-T Receive Interface Figure 39. 1000BASE-T Receive Interface Timing RX_CLK RxDV RXD[7:0] Table 50. GMII 1000BASE-T Receive Signal Parameters Symbol RXD[7:0], RX_DV, RXER Setup to Rx_CLK High RXD[7:0], RX_DV, RXER Hold after Rx_CLK High 1.
  • Page 144: Serdes Ac Timing Specification

    Table 51. SerDes Timing Parameters Symbol Transmit eye width Receiver eye width Transmit amplitude Receiver amplitude Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Parameter Units – – 1000 – –...
  • Page 145: Mdio Ac Timing Specification

    IXF1104 4-Port Gigabit Ethernet Media Access Controller MDIO AC Timing Specification The MDIO Interface on the IXF1104 MAC can operate in two modes – low-speed and high-speed. In low-speed mode, the MDC clock signal operates at a frequency of 2.5 MHz. In high-speed mode, the MDC clock signal operates at a frequency of 18 MHz.
  • Page 146: Mdio Ac Timing

    MDC to MDIO Output delay 1. Typical values are at 25 testing. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller MA X Symbol – – – – – –...
  • Page 147: Optical Module And I 2 C Ac Timing Specification

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Optical Module and I 7.7.1 C Interface Timing Figure 45 Figure 46 AC timing characteristics. Figure 45. Bus Timing Diagram C_Clk HD.STA C_Data In C_Data Out Figure 46. Write Cycle Diagram...
  • Page 148: Datasheet

    Stop setup time SU.STO Data out hold time Write cycle time Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Parameter Units – µs – µs – – µs –...
  • Page 149: Cpu Ac Timing Specification

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller CPU AC Timing Specification 7.8.1 CPU Interface Read Cycle AC Timing Figure Figure 48, and Figure 47. CPU Interface Read Cycle AC Timing uPx_ADD[12:0] uPx_CsN uPx_RdN uPx_Data[31:0] uPx_RdyN 7.8.2 CPU Interface Write Cycle AC Timing Figure 48.
  • Page 150: Cpu Interface Write Cycle Ac Signal Parameters

    Write data sampling delay Tcyd Ready width in write cycle Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Parameter 5 ns – 10 ns – 10 ns – 24 ns –...
  • Page 151: Transmit Pause Control Ac Timing Specification

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Transmit Pause Control AC Timing Specification Figure 49 Table 55 interface operates as an asynchronous interface relative to the main system clock (CLK125). There is, however, a relationship between the TXPAUSEADD bus and the strobe signal (TXPAUSEFR).
  • Page 152: Jtag Ac Timing Specification

    TMS/TDI hold from TCLK Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller provide the JTAG AC timing specifications. Parameter Units 0.4 x Tjc 0.6 x Tjc 0.4 x Tjc...
  • Page 153: System Ac Timing Specification

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.11 System AC Timing Specification Figure 51 Table 57 Figure 51. System Reset AC Timing Table 57. System Reset AC Timing Parameters Symbol Reset pulse width Reset recovery time illustrate the system reset AC timing specifications.
  • Page 154: Led Ac Timing Specification

    Tlatl LED_CLK falling edge to LED_LATCH falling edge Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller provide the LED AC timing specifications. Tcyc Tlow Tdatd Parameter Thatl Tlath Units 1.36...
  • Page 155: Register Set

    CPU interface packs or unpacks the partial accesses into a 32-bit register value. Graphical Representation Figure 53 represents an overview of the IXF1104 MAC global control status registers that are used to configure or report on all ports. All register locations shown in double word.
  • Page 156: Per Port Registers

    The address vector for the IXF1104 MAC is 11 bits wide. This allows for 7 bits of port-specific access and a 4-bit vector to address each port and all global registers. The address format is shown Figure Figure 54.
  • Page 157: Mac Rx Statistics Registers ($ Port Index + Offset)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 2 of 2) Register “Max Frame Size (Addr: Port_Index + 0x0F)” “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)”...
  • Page 158: Mac Tx Statistics Registers ($ Port Index + Offset)

    TxExcessiveLengthDrop TxUnderrun TxTagged TxCRCError TxPauseFrames TxFlowControlCollisionsSend Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Bit Size Bit Size Mode Ref Page Offset 0x33 0x34 0x35 0x36 0x37 0x38 0x39...
  • Page 159: Phy Autoscan Registers ($ Port Index + Offset)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 62. PHY Autoscan Registers ($ Port Index + Offset) Register “PHY Control ($ Port Index + 0x60)” “PHY Status ($ Port Index + 0x61)” “PHY Identification 1 ($ Port Index + 0x62)”...
  • Page 160: Tx Fifo Registers ($ 0X600 - 0X63E)

    TX FIFO Low Watermark Port 2 TX FIFO Low Watermark Port 3 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Bit Size Bit Size Mode Ref Page Address 0x58D –...
  • Page 161: Mdio Registers ($ 0X680 - 0X683)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 2 of 2) Register Reserved TX FIFO MAC Threshold Port 0 TX FIFO MAC Threshold Port 1 TX FIFO MAC Threshold Port 2...
  • Page 162: Serdes Registers ($ 0X780 - 0X798)

    “I C Data Ports 0 - 3 ($0x79F)” Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Bit Size Bit Size Bit Size Mode Ref Page Address – 0x702 - 0x709 0x70A –...
  • Page 163: Mac Control Registers

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.1 MAC Control Registers Table 70 through Table 92 “Port Multicast Address ($ Port_Index +0x1A – +0x1B)” on page 173 provide details on the control and status registers associated with each MAC port. The register address is ‘Port_index + 0x**’, where the port index is set at any value from 0x0 through 0x5.
  • Page 164: Collision Distance ($ Port_Index + 0X05)

    R/W/C = Read/Write, Clear on Write Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Description Description Description The lowest 32 bits of the 48-bit globally assigned multicast pause frame destination address.
  • Page 165: Ipg Receive Time 1 ($ Port_Index + 0X0A)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A) Name This timer is used during half-duplex operation when there is a packet waiting for transmission from the MAC. This timer starts after CRS is de-asserted.
  • Page 166: Pause Threshold ($ Port_Index + 0X0E)

    1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Description Address Type Default Port_Index 0x0000002F...
  • Page 167: Mac If Mode And Rgmii Speed ($ Port_Index + 0X10)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10) Name Register Description – MAC IF Mode: Determines the MAC operation frequency and mode per port. Changes to the data setting of this register must be made in conjunction with the Interface Mode Change Enable Ports 0 - 3 ($0x794)"...
  • Page 168: Fc Enable ($ Port_Index + 0X12)

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved When TX HDFC is enabled (half-duplex mode only), the MAC generates deliberate collisions on incoming packets when the RX FIFO occupancy crosses the High Watermark (flow control).
  • Page 169: Short Runts Threshold ($ Port_Index + 0X14)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 86. Short Runts Threshold ($ Port_Index + 0x14) Name The 5-bit configuration holds the value in bytes, which applies to the threshold in determining between runts and short. The bits 4:0 of this register are alone used.
  • Page 170: Tx Config Word ($ Port_Index + 0X17)

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description 0 = Receiving idle/data stream 1 = Receiving /C/ ordered sets 0 = RxConfigWord has changed since last read 1 = RxConfigWord has not changed since last read.
  • Page 171: Diverse Config Write ($ Port_Index + 0X18)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 2 of 2) Name 13:12 Remote Fault [1:0] 11:9 Reserved Asym Pause Sym Pause Half Duplex Full Duplex Reserved 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 172: Rx Packet Filter Control ($ Port_Index + 0X19)

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Write as 1, ignore on Read. Write as 0, ignore on Read. Write as 1, ignore on Read. Description “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2...
  • Page 173: Port Multicast Address ($ Port_Index +0X1A – +0X1B)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2) Name B/Cast Drop En M/Cast Match En U/Cast Match En 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 174: Mac Rx Statistics Register Overview

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Counts the bytes received in all legal frames, including all bytes from the destination MAC address to and including the cyclic redundancy check (CRC).
  • Page 175: Datasheet

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 2 of 4) Name Description The total number of packets received (including RxPkts65to127 bad packets) that were 65-127 octets in length.
  • Page 176: Datasheet

    Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Frames with a legal frame size, but containing less than eight additional bits. This occurs when the frame is not byte aligned. The CRC of the frame is wrong when the additional bits are stripped.
  • Page 177: Datasheet

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 4 of 4) Name Description The total number of packets received that are less than 64 octets in length, but longer than or...
  • Page 178: Mac Tx Statistics Register Overview

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Counts the bytes transmitted in all legal frames. The count includes all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted.
  • Page 179: Datasheet

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 2 of 4) Name TxBCPkts TxPkts64Octets Txpkts65to127Octets Txpkts128to255Octets Txpkts256to511Octets Txpkts512to1023Octets Txpkts1024to1518Octets Txpkts1519toMaxOctets TxDeferred TxTotalCollisions 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 180: Datasheet

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description A count of successfully transmitted frames on a particular interface where the transmission is inhibited by exactly one collision. A frame that is counted...
  • Page 181: Phy Autoscan Registers

    NOTE: NA - half-duplex only 103) is enabled and the IXF1104 MAC is configured in copper Description Reserved PHY Soft Reset. Resets the PHY registers to their default value.
  • Page 182: Phy Status ($ Port Index + 0X61)

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description 0 = Disable auto-negotiation process 1 = Enable auto-negotiation process This register bit must be enabled for 1000BASE-T operation. 0 = Normal operation...
  • Page 183: Phy Identification 1 ($ Port Index + 0X62)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 96. PHY Status ($ Port Index + 0x61) (Sheet 2 of 2) Name 10 Mbps Half-Duplex 100BASE-T2 Full-Duplex 100BASE-T2 Half-Duplex Extended Status Reserved MF Preamble Suppression Reserved Remote Fault Auto-Negotiation...
  • Page 184: Phy Identification 2 ($ Port Index + 0X63)

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved The PHY identifier is composed of register bits 24:19 of the OUI (Organizationally Unique Identifier) Six bits containing the manufacturer’s part number Four bits containing the manufacturer’s revision...
  • Page 185: Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0X65)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 2 of 2) Name 10BASE-T Full-Duplex 10BASE-T Half-Duplex Selector Field, S[4:0] 1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write Table 100.
  • Page 186: Auto-Negotiation Expansion ($ Port Index + 0X66)

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description 0 = Link partner is not 100BASE-TX, full-duplex mode capable 1 = Link partner is 100BASE-TX, full-duplex mode capable 0 = Link partner is not 100BASE-TX, half-duplex...
  • Page 187: Auto-Negotiation Next Page Transmit ($ Port Index + 0X67)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66) (Continued) (Sheet 2 of 2) Name Next Page Able Page Received Link Partner Auto- Negotiation Able 1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write Table 102.
  • Page 188: Global Status And Configuration Register Overview

    Table 103. Port Enable ($0x500) Name Register Description: A control register for each port in the IXF1104 MAC. Port ID = bit position in the register. To make a port active, the bit must be set High. For example, Port 2 active implies a register value of 0000.0100.
  • Page 189: Link Led Enable ($0X502)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 105. Link LED Enable ($0x502) Name Register Description: Per port bit should be set upon detection of link to enable proper operation of the link LEDs. 31:4 Reserved Link LED Enable Port 3...
  • Page 190: Mdio Soft Reset ($0X506)

    R/W/C = Read/Write, Clear on Write Table 108. CPU Interface ($0x508) Name Register Description: CPU Interface Endian select. Allows the user to select the Endian of the CPU interface to allow for various CPUs to be connected to the IXF1104 MAC. 31:25 Reserved CPU Endian...
  • Page 191: Led Flash Rate ($0X50A)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 110. LED Flash Rate ($0x50A) Name Register Description: Global selection of LED flash rate. 31:3 Reserved LED Flash Rate Control 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 192: Jtag Id ($0X50C)

    R/W/C = Read/Write, Clear on Write 2. These bits vary with stepping. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Version Part ID JEDEC Continuation Characters JEDEC ID Fixed Type...
  • Page 193: Rx Fifo Register Overview

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.6 RX FIFO Register Overview Table 113 through Table 131 FIFO High and Low watermarks. Table 113. RX FIFO High Watermark Port 0 ($0x580) Name Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This equates to 1840 bytes of data.
  • Page 194: Rx Fifo High Watermark Port 3 ($0X583)

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved The high water mark value. NOTE: Must be greater than the RX FIFO Low Watermark and RX FIFO transfer threshold.
  • Page 195: Rx Fifo Low Watermark Port 2 ($0X58C)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 119. RX FIFO Low Watermark Port 2 ($0x58C) Name Register Description: The default value of 0x072 represents 114 eight-byte locations. This equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the...
  • Page 196: Rx Fifo Port Reset ($0X59E)

    R/W/C = Read/Write, Clear on Write Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved Port 3 0 = De-assert reset 1 = Reset Port 2 0 = De-assert reset...
  • Page 197: Rx Fifo Overflow Event ($0X5A0)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 2 of 2) Name RX FIFO Errored Frame Drop Enable Port 2 RX FIFO Errored Frame Drop Enable Port 1 RX FIFO Errored...
  • Page 198: Rx Fifo Errored Frame Drop Counter Ports 0 - 3 ($0X5A2 - 0X5A5)

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description This register counts all frames dropped from the RX FIFO for port 0 by meeting one of the following conditions: •...
  • Page 199: Rx Fifo Spi3 Loopback Enable For Ports 0 - 3 ($0X5B2)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 2 of 2) Name RX FIFO Errored Frame Drop Counter on Port 2 RX FIFO Errored...
  • Page 200: Rx Fifo Padding And Crc Strip Enable ($0X5B3)

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved CRC stripping is enabled for Port 3. 0 = Disabled 1 = Enabled CRC stripping is enabled for Port 2.
  • Page 201: Rx Fifo Transfer Threshold Port 0 ($0X5B8)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8) Name Register Description: RX FIFO transfer threshold for port 0 in 8-byte location. 31:12 Reserved RX FIFO Transfer 11:0 Threshold - Port 0 1.
  • Page 202: Rx Fifo Transfer Threshold Port 2 ($0X5Ba)

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved RX FIFO transfer threshold for port 2. This must be less than the RX FIFO High water mark. User definable control register that sets the...
  • Page 203: Tx Fifo Register Overview

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.7 TX FIFO Register Overview Table 132 through Table 139 FIFO High and Low watermark. Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) Name Description High watermark for TX FIFO Port 0. The default value of 0x3E0 represents 992 8-byte locations.
  • Page 204: Tx Fifo Low Watermark Register Ports 0 - 3 ($0X60A – 0X60D)

    1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Address Type Default 0x60A 0x000000D0 0x60B 0x000000D0...
  • Page 205: Tx Fifo Mac Threshold Register Ports 0 - 3 ($0X614 – 0X617)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617) Name Description MAC threshold for TX FIFO Port 0. The default value of 0x1BE represents 446 8-byte locations.
  • Page 206: Tx Fifo Overflow/Underflow/Out Of Sequence Event ($0X61E)

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved Port 3 0 = FIFO out of sequence event did not occur 1 = FIFO out of sequence event occurred...
  • Page 207: Loop Rx Data To Tx Fifo (Line-Side Loopback) Ports 0 - 3 ($0X61F)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 2 of 2) Name FOE2 FOE1 FOE0 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 208: Tx Fifo Overflow Frame Drop Counter Ports 0 - 3 ($0X621 – 0X624)

    R/W/C = Read/Write, Clear on Write Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Port 2 0 = De-assert Reset 1 = Assert Reset Port 1 0 = De-assert Reset...
  • Page 209: Tx Fifo Errored Frame Drop Counter Ports 0 - 3 ($0X625 – 0X629)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629) Name Description This register provides the number of packets dropped by the TX FIFO due to the following:...
  • Page 210: Tx Fifo Occupancy Counter For Ports 0 - 3 ($0X62D – 0X630)

    Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description This register gives the Occupancy for TX FIFO Port 0. This is a Read only register This register gives the Occupancy for TX FIFO Port 1.
  • Page 211: Mdio Register Overview

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.8 MDIO Register Overview Table 142 through Table 145 Table 142. MDIO Single Command ($0x680) Name Register Description: Gives the CPU the ability to perform single MDIO read and write accesses to the external PHY for ports that are configured in copper mode.
  • Page 212: Autoscan Phy Address Enable ($0X682)

    R/W/C = Read/Write, Clear on Write Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description Reserved Autoscan PHY address enable 0 = Disable address 1 = Enable address Description Reserved MDIO progress.
  • Page 213: Spi3 Register Overview

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.9 SPI3 Register Overview Table 146 through Table 148 “Address Parity Error Packet Drop Counter ($0x70A)” on page 219 provide an overview of the SPI3 registers. Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 1 of 3)
  • Page 214: Datasheet

    Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description SPHY/MPHY Mode: Indicates whether to drop packets with data parity error for port 0. 0 = Do not drop packets with data parity error...
  • Page 215: Spi3 Receive Configuration ($0X701)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 3 of 3) Name Tx_port_enable Port 2 Tx_port_enable Port 1 Tx_port_enable Port 0 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 216: Datasheet

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description SPHY Mode: Indicates the number of pause cycles to be introduced between back-to-back transfers for port 1. 0 = Zero pause cycles...
  • Page 217: Datasheet

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 147. SPI3 Receive Configuration ($0x701) (Continued) (Sheet 3 of 4) Name Rx_parity_sense Port 3 Rx_parity_sense Port 2 Rx_parity_sense Port 1 Rx_parity_sense Port 0 Rx_port_enable Port 3 Rx_port_enable Port 2 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;...
  • Page 218: Datasheet

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Description SPHY Mode: 0 = Disables the selected SPI3 RX port. 1 = Enables the selected SPI3 RX port. MPHY Mode: 0 = Disables the selected SPI3 RX port.
  • Page 219: Address Parity Error Packet Drop Counter ($0X70A)

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 148. Address Parity Error Packet Drop Counter ($0x70A) Name Register Description: This register counts the number of packets dropped due to parity error detection during the address selection cycle. 31:8...
  • Page 220: Serdes Register Overview

    221 define the contents of the SerDes registers at base location 0x780, which contain the control and status for the four SerDes interfaces on the IXF1104 MAC. Table 149. TX Driver Power Level Ports 0 - 3 ($0x784) Name Register Description: Allows selection of various programmable drive strengths on each SerDes port.
  • Page 221: Clock And Interface Mode Change Enable Ports 0 - 3 ($0X794)

    Register Description: This register is used when a change to the operational mode or speed of the IXF1104 MAC is required. This register ensures that when a change is made that the internal clocking of the IXF1104 MAC is managed correctly and no unexpected effects of the operational or speed change are observable on the line interfaces.
  • Page 222: Optical Module Register Overview

    Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller C Data Ports 0 - 3 ($0x79F)” on page 223 Description Reserved Rx_LOS inputs for Ports 0-3 Reserved Tx_FAULT inputs for Ports 0-3...
  • Page 223: Datasheet

    C Data Ports 0 - 3 ($0x79F) Name Register Description: These registers hold data bytes that are read and written using the I interface to Optical Module Interfaces connected to each port of the Intel Gigabit Ethernet Media Access Controller. 31:24...
  • Page 224: Mechanical Specifications

    Mechanical Specifications The IXF1104 MAC is packaged in a 576-ball BGA package with 6 balls removed diagonally from each corner, for a total of 552 balls used measuring 25 mm x 25 mm. The pitch of the package balls is 1 mm.
  • Page 225: Package Information

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Package Information 9.3.1 CBGA Package Diagrams Figure 55 Figure 56 Figure 55. CBGA Package Diagram Note: All dimensions are in mm. Chip Carrier A01 Corner Note: All dimensions are in mm.
  • Page 226: Cbga Package Side View Diagram

    Figure 56. CBGA Package Side View Diagram Note: All dimensions are in mm. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 45L4867 (552) Solder ball C4 Encapsulant Fillet Chip 0.81 ± 0.1 (2.47 Max) (2.03 Min)
  • Page 227: Flip Chip-Plastic Ball Grid Array Package Diagram

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller 9.3.2 Flip Chip-Plastic Ball Grid Array Package Diagram Figure 57 illustrates the FC-PBGA top and bottom package views and PBGA mechanical specifications. Note: Please contact your field sales representative for more information on the FC-PBGA package.
  • Page 228: Fc-Pbga Mechanical Specifications

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 58. FC-PBGA Mechanical Specifications Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005...
  • Page 229: Top Label Marking Example

    IXF1104 4-Port Gigabit Ethernet Media Access Controller 9.3.3 Top Label Marking Example Figure 59 shows the IXF1104 MAC non-RoHS-compliant device marking label. Note: In contrast to the Pb-Free (RoHS-compliant) package, the non-RoHS-compliant package does not have the “e1” symbol. Figure 59. Package Marking Example...
  • Page 230: Product Ordering Information

    1. Please contact your field sales representative for detailed information on the FC-PBGA package. Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller provide IXF1104 MAC product ordering information. Package RoHS- Revision Type Compliant CBGA...
  • Page 231: Ordering Information – Sample

    ® Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 60. Ordering Information – Sample 1104 Product Revision xn = 2 Alphanumeric characters Temperature Range A = Ambient (0 – 55 C = Commercial (0 – 70 E = Extended (-40 – 85...

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