Mphy Receive Logical Timing; Mphy 32-Bit Interface; Datasheet - Intel IXF1104 Datasheet

Figure 12. MPHY Receive Logical Timing
RFCLK
REN
RSX
RSOP
RMOD
[1:0]
RERR
RSX
RDAT
[31:0]
RPRTY
RVAL
Figure 13. MPHY 32-Bit Interface
Network Processor

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
0000 1- 3 4- 7
SPI3 Bus
TFCLK
TENB
TDAT[31:0]
TMOD[1:0]
TPRTY
TSOP
TEOP
TERR
TSX
DTPA_0:3
STPA
PTPA
TADR[1:0]
RFCLK
RENB
RDAT[31:0]
RMOD[1:0]
RPRTY
RVAL
RSOP
REOP
RERR
RSX
1- 3 48- 51 52- 55
IXF1104 MPHY
Line-Side Interface
Mode
TFCLK
TENB_0
Port 0
TDAT[31:0]
TMOD[1:0]
TPRTY_0
TSOP_0
TEOP_0
Port 1
TERR_0
TSX
DTPA_0:3
STPA
PTPA
Port 2
TADR[1:0]
RFCLK
RENB_0
RDAT[31:0]
Port 3
RMOD[1:0]
RPRTY RPRTY_0
RVAL_0
RSOP_0
REOP_0
RERR_0
RSX
56- 59 60- 63 00001 0- 3
3217-02
Transceiver
Transceiver
Transceiver
Transceiver
B0660-02
86