41210 Bridge Reset And Power Timing Considerations; A_Rst#,B_Rst# And Perst# Timing Requirements; Vcc15 And Vcc33 Voltage Requirements - Intel 41210 Design Manual

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41210 Bridge Reset and Power Timing

Considerations

This chapter describes the 41210 Bridge reset timing considerations.

5.1

The PCI-X Specification requires that there is a 100ms delay from valid power (PERST#) to reset

deassertion (A_RST#/B_RST#). 41210 Bridge will keep A_RST#/B_RST# asserted for a

minimum of 320ms after PERST# is deasserted.

5.2

The following steps are the power sequencing requirements that must be followed with the

41210 Bridge:

1. The 41210 Bridge requires that the VCC33 voltage rail be no less than 0.5V below VCC15

(absolute voltage value) at all times during 41210 operation, including during system power

up and power down. In other words, the following must always be true:

VCC33 >= (VCC15 – 0.5V)

This can be accomplished by placing a diode (with a voltage drop <0.5V) between VCC15 and

VCC33. A node will be connected to VCC15 and cathode will be connected to VCC33.

If VCC15 (1.5V PCI-X I/O voltage) and VCC15 (1.5V core voltage) are tied together on the

platform, then both voltages must meet the above rule.

Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies.

2. If a voltage regulator solution is used which shunts VCC15 to ground while VCC33 is

powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is

fully powered is 20ms.

3. The maximum allowed time between VCC33 and VCC15 ramping is 525ms.

Note: There is no minimum sequencing time requirement other than requirements in Steps 2 and 3.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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