HP 64751 User Manual page 484

Chapter 13: Specifications and Characteristics
Emulator Specifications and Characteristics
AC Electrical Specifications (64751-66508 and higher active probe board numbers) — Read and
Write Cycles
(Vcc = 5.0 Vdc +/-5%; GND = 0 Vdc; T
Num. Characteristic
56 RESET Pulse Width (Reset Instruction)
57 BERR Negated to HALT Negated (Rerun)
70 CLKOUT Low to Data Bus Driven (Show
Cycle)
71 Data Setup Time to CLKOUT Low (Show
Cycle)
72 Data Hold from CLKOUT Low (Show Cycle) t
MC68340 NOTES:
1. All AC timing is shown with respect to 0.8-V and 2.0-V levels unless otherwise noted.
2. This number can be reduced to 5 ns if strobes have equal loads.
3. If multiple chip selects are used, the CS width negated (#15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select.
4. These hold times are specified with respect to DS on asychronous reads and with respect to CLKOUT
on synchronous reads. The user is free to use either hold time.
5. If the asychronous setup time (#47) requirements are satisfied, the DSACKx low to data setup time
(#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the
data-in to CLKOUT low setup time (#27) for the following clock cycle, BERR must only satisfy the late
BERR low to CLKOUT low setup time (#27A) for the following clock cycle.
6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until
after cycles of the current operand transfer are complete and RMC is negated.
7. In the absence of DSACKx, BERR is an asychronous input using the asychronous setup time (#47).
8. Address Access Time = 2t
Access Time = 2t - t
cyc CLSA
HP 64751 NOTES:
A. IFETCH and IPIPE are not driven to the target system.
B. The emulator does not respond to BKPT from the target system.
C. The emulator does not drive data to the target system during show cycles.
484
= T to T
A L H
+ t - t - t
cyc CW CHAV DICL
- t = 55 ns (@ 25.16-MHz clock).
DICL
)
MC68340
25.16 MHz
Symbol Min Max
t 512 —
HRPW
t 0 —
BNHN
t 0 30
SCLDD
t 10 —
SCLDS
6 —
SCLDH
= 74 ns (@ 25.16-MHz clock). Chip Select
HP 64751
Min Max Unit
512 — clks
0 — ns
C C
— — ns
C
— — ns
C
— — ns