HP 64751 User Manual page 156

Chapter 6: Using the Emulator
Using the Emulator Configuration Registers
In the previous figure, there is a block labeled DE-SIM module. It receives as
inputs from the 68340:
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•
The DE-SIM module provides as outputs:
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•
The 68340 SIM is configured through the registers in the SIM register class; these
registers control how the 68340 uses external signal lines to access memory.
The emulator's DE-SIM module is configured through the registers in the CF_SIM
register class. The DE-SIM module controls how the emulator interprets the
signals from the 68340 when accessing emulation memory and passing information
to the analysis trace.
Normally, the SIM and CF_SIM registers should be programmed with the same
values so they will be working together.
One of the primary functions of the DE-SIM is to provide A31-A24 to the memory
mapper and analyzer so they will have the complete 32-bit address bus. This is
easy if Port A of the 68340 is programmed as address lines; however, if it's
programmed as an input port, for example, the upper address lines are not available
external to the 68340 (this is the case following reset). The four chip selects,
however, have access to the full 32 bit address inside the 68340. You can therefore
locate memory using a chip select at an address that is not possible to decode
externally. If properly programmed, the DE-SIM can use information in the
programming of the chip selects to re-create the upper address lines. This provides
the ability to map emulation memory at these addresses and also provides a correct
address in the analysis trace so that symbolic debugging is possible.
Normally, the DE-SIM would be programmed through the CF_SIM registers to
match the programming of the 68340 SIM as it will exist after all of the boot-up
configuration is complete. This can be done before the boot-up code is run. In fact,
the programming of the CF_SIM registers is part of the configuration and will be
loaded along with the memory map and other configuration items when a
configuration file is loaded.
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Port A which can be address lines 31-24, interrupt acknowledge inputs, or
general purpose I/O lines.
Port B which can be interrupt requests, chip selects, or general purpose I/O
lines.
Address lines A31-A24 to the memory mapper and the analyzer.
A qualified chip select 0 (CS0) to the memory mapper.