Boundary-Scan Register - Intel PXA27 Series Design Manual

JTAG Debug
26.4.4.2

Boundary-Scan Register

The boundary-scan register consists of a set of serially connected cells around the periphery of the
PXA27x processor at the interface between the core logic and the PXA27x processor I/O pins. This
register isolates the pins from the core logic and then drive or monitor the pins. The connected
boundary-scan cells make up a shift register.
See Table 26-4
register.
Table 26-4. I/O Pins Excluded from Boundary-Scan Register
Pin
PXTAL_IN
PXTAL_OUT
TXTAL_IN
TXTAL_OUT
PWR_EN
ALL VDD/VSS pins
PWR_OUT
nRESET_OUT
TCK
TMS
TDI
TDO
nTRST
The boundary scan logic powers down when nBATT_FAULT, nVCC_FAULT, or nRESET is
asserted (low) and when the PXA27x processor device is in sleep or deep sleep. Refer to
"Clocks and Power Manager Unit,"
for details of sleep and deep-sleep modes. Thus, nBATT_FAULT, nVCC_FAULT, and nRESET
must be driven high (de-asserted) for any instruction that uses the boundary-scan register.
The boundary-scan register is selected as the register to be connected between TDI and TDO only
during the sample/preload and extest instructions. Values in the boundary-scan register are used but
are not changed during the clamp instruction.
During normal (system) operation, straight-through connections between the core logic and pins
are maintained, and normal system operation is unaffected. This is also the case when the sample/
preload instruction is selected.
In test mode when extest is the currently selected instruction, values are applied to the output pins
independently of the actual values on the input pins and core logic outputs. In the PXA27x
processor, all of the boundary-scan cells include update registers. Refer to the IEEE 1149.1
standard for more information on the update registers.
The values stored in the boundary-scan register after power-up are not defined. The values
previously clocked into the boundary-scan register are not guaranteed to be maintained across a
JTAG reset (from forcing nTRST low or entering the Test-Logic-Reset state).
II:26-8
for the list of the PXA27x processor I/O pins that are not part of the boundary-scan
Reason for Exclusion
Prevents disruption of processor clocks and power
Prevents disruption of power and unintentional reset
for external components
Prevents disruption of the TAP-controller JTAG
interface
in the Intel
®
PXA27x Processor Family Developers Manual
®
Intel PXA27x Processor Family Design Guide
Chapter 3,