Vlio Memory Signals; Vlio Memory Interface Signals - Intel PXA27 Series Design Manual

System Memory Interface
6.5.5.1

VLIO Memory Signals

See Table 6-12
Table 6-12. VLIO Memory Interface Signals
Signal Name
nCS<5:0>
MA<25:0>
MD<31:0>
DQM<3:0>
nWE
nOE
RDY
RDnWR
II:6-22
for the list of signals required to interface to VLIO memory devices.
Direction Polarity

VLIO Memory Interface Signals

Output Active Low
Output NA
Bidirectional NA
Output Active High
Output Active Low
Output Active Low
Input Active High
Miscellaneous I/O Signals
Output Active High
Description
Chip selects for static memory
Output address to all memory types
NOTE: Do not use MA0 for byte addressing because all
VLIO devices must have a minimum bus width of
16 bits when interfacing to the PXA27x processor
memory controller. Use MA0 to address the upper
64 Mbytes of memory within a 128 Mbytes partition.
Bidirectional data for all memory types
Data byte mask control
DQM<0> corresponds to MD<7:0>
DQM<1> corresponds to MD<15:8>
DQM<2> corresponds to MD<23:16>
DQM<3> corresponds to MD<31:24>
0 = Do not mask out corresponding byte
1 = Mask out corresponding byte
Write enable for VLIO memory
Output enable for Static Memory
Variable Latency I/O signal for inserting wait states
0 = Wait
1 = VLIO is ready
Data direction signal to be used by output transceivers
0 = MD<31:0> is driven by the PXA27x processor
1 = MD<31:0> is not driven by the PXA27x processor
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Intel PXA27x Processor Design Guide