Spi Protocol Block And Schematic Diagrams; Spi Protocol Layout Notes - Intel PXA27 Series Design Manual

MultiMediaCard/SD/SDIO Card Controller
15.4.3.2

SPI Protocol Block and Schematic Diagrams

See Figure 15-5
controller and the following devices:
•
Two MMC devices
•
Two SD Cards
•
Two SDIO Cards
•
A maximum of two mixed type devices
The block diagram shows high-level signal usage and connectivity when using the SPI
communication protocol with the specified devices.
Figure 15-5. SPI Protocol Interface Block Diagram
See Figure 15-2
SPI mode communication with an MMC device.
See Figure 15-4
supporting SPI mode communication with an SD or SDIO Card.
15.4.3.3

SPI Protocol Layout Notes

The PXA27x processor signals MMCLK, MMCMD, and MMDAT<0> are connected in parallel to
both device sockets for dual device SPI mode operation. MMCCS<0> and MMCCS<1> are used
as chip selects only in SPI mode and connect separately to the respective chip select signals of the
socket.
II:15-12
for the block diagram showing the interface between the MMC/SD/SDIO Card
PXA27x
Processor
MMC/SD/SDIO
Controller
(SPI Mode)
MMCLK
MMCMD
MMDAT<0>
MMDAT<1>
MMDAT<2>/MMCCS<0>
MMDAT<3>/MMCCS<1>
for illustration of an MMC socket-based schematic diagram capable of supporting
for illustration of an SD/SDIO Card socket-based schematic diagram capable of
Clock
Command
Write Data
Response
Read Data
* Only applies for SDIO devices.
§§
®
Intel PXA27x Processor Family Design Guide
MMC
Devices
in SPI Mode
or
SD/SDIO
Cards in SPI
Mode
(2 Max)
CLK
CMD
DAT
SDIO Interrupts*
Device_0
Select
Device_1
Select
MMC_003_P2