Channel Access/Control Block; Pxa25X Compatibility Channels 0-3 Block; Signals ............................................................................................Ii: - Intel PXA27 Series Design Manual

OS Timer Interface
22.3 Block Diagram
See the block diagram of the OS Timer Controller in
Figure 22-1. OS Timer Block Diagram
22.3.1

Channel Access/Control Block

This block controls reads and writes to registers within the operating system timers block. It is also
responsible for maintaining the OS Match Control Registers (OMCR4 - OMCR11) and generating
the appropriate clocks and control signals for each timer channel.
22.3.2

PXA25x Compatibility Channels 0-3 Block

This block maintains the four Intel
generating the appropriate channel-match signals.
II:22-2
CLK_3.25M
Read / Write
Data & Control
CLK_32K
Channel
CLK_13M
Access/
CLK_EXT
Control
EXT_SYNC<1:0>
®
Figure 22-1.
M0
PXA25x
Compatiblity M1
Channels 0-3
M2
M3
Channel 4
M4
Channel 5
M5
Channel 6
M6
Channel 7
M7
Channel 8
M8
Channel 9
M9
Channel 10
M10
Channel 11
M11
PXA25x processor-compatible timer channels and for
®
Intel PXA27x Processor Family Design Guide
CH_OUT<1:0>
(External)
WDOG_RST
(Internal)
Output
OST_0_Match_INT
Control
(Internal)
OST_1_Match_INT
(Internal)
OST_2_Match_INT
(Internal)
OST_3_Match_INT
(Internal)
OST_4:11_Match_INT
(Internal)
OST_001_P2