Block Diagram - Intel PXA27 Series Design Manual

27.4

Block Diagram

See Figure 27-1
processor and an image sensor module. It is important to note that master mode refers to the case
where the sensor module drives the line and frame synchronization signals. Slave mode is the case
where the PXA27x processor drives the line and frame synchronization signals. See
for an interface options summary.
Figure 27-1. Block Diagram for 8-bit Master Parallel Interface
Image Sensor
Module
®
Intel PXA27x Processor Family Design Guide
for illustration of a typical 8-bit master parallel connection between the PXA27x
D0
D1
D2
D3
D4
D5
D6
D7
CLK
PCLK
VSYNC
HSYNC
RESET
PDWN
SDL
SDA
Intel® Quick Capture Technology
Figure 27-2
PXA27x
Processor
CIF_DD[0]
CIF_DD[1]
CIF_DD[2]
CIF_DD[3]
Quick
CIF_DD[4]
CIF_DD[5] Capture
CIF_DD[6]
Interface
CIF_DD[7]
CIF_MCLK
CIF_PCLK
CIF_FV
CIF_LV
GPIO X
GPIO Y
SDL
SDA
II: 27-3