Block Diagram; Layout Notes - Intel PXA27 Series Design Manual

DMA Controller Interface
5.3

Block Diagram

See the block diagram for the DMA controller in
Figure 5-1. DMA controller Block Diagram
DVAL(1:0)
(external)
Bridge
Peripheral bus (internal)
5.4

Layout Notes

The DREQ<2:0> signals must remain asserted for four CLK_MEM cycles for the DMA to
recognize the low to high transition. When de-asserted, the DREQ<2:0> signals must remain de-
asserted for at least four CLK_MEM cycles.
Refer to the Intel
®
Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for all AC
timing information.
II:5-2
Memory Controller
Internal bus (internal)
DMA Controller
DREQ(2:0)
(external)
PREQ(67:0)
(internal)
®
PXA270 Processor Electrical, Mechanical, and Thermal Specification and
Figure 5-1.
DMA Descriptor Controller
32 DMA Channels
Control Registers
Channel 31
DINT
Channel 0
DDADR0
DSADR0
DCSR
DTADR0
DCMD0
DRCMR
®
Intel PXA27x Processor Family Design Guide
DMA_IRQ
(internal)