Nvdd_Fault - Intel PXA27 Series Design Manual

3.2.3 Power Enable (PWR_EN)
PWR_EN is an active-high output from the PXA27x processor (input to the PMIC) that enables the
external core power supplies (VCC_CORE, VCC_SRAM, VCC_PLL.) De-asserting PWR_EN
indicates to the external regulator that the processor is going into sleep mode and that the low-
voltage core power supplies are removed.
When PWR_EN is asserted, normal operation resumes and the PMIC turns on the core (low-
voltage) supplies. The power controller must preserve, during sleep or deep sleep, the previous
state of its regulators including the voltage for the core. Then, on resumption of core power, the
regulators return to their last known voltage levels.
3.2.3.1 System Power Enable (SYS_EN)
SYS_EN is an active-high output from the PXA27x processor (input to the PMIC) that enables the
external system power supplies. De-asserting SYS_EN indicates to the power supply that the
processor is going into deep sleep mode, allowing the removal of high-voltage system power
supplies (VCC_IO, VCC_LCD, VCC_MEM, VCC_USIM, VCC_BB, and VCC_USB). When
powering on and off the various voltage domains, assertion and de-assertion of SYS_EN must
occur in the correct sequence with PWR_EN to ensure the correct sequencing of power supplies.
When SYS_EN is asserted, normal operation resumes and the PMIC turns on the system I/O (high-
voltage) supplies. Then, when PWR_EN is asserted, the PMIC turns on the core (low-voltage)
supplies. The power controller must return all system I/O voltages to their pre-deep sleep mode
levels.
3.2.3.2 Power Manager I
The PWR_SCL signal is the power manager I
bus must operate at a minimum 40 KHz and optionally be capable of operating at 160 KHz clock
rate.
3.2.3.3 Power Manager I
The PWR_SDA signal is the power manager I
open-drain signal so that either component pulls it down to a logic-low level.
3.2.3.4

nVDD_FAULT

nVDD_FAULT signals the PXA27x processor that one or more of its currently enabled supplies
are below the minimum regulation limit (supplies that are not enabled, do not cause
nVDD_FAULT assertion.) Functionally, nVDD_FAULT indicates to the processor when it is safe
to exit sleep or when it must enter sleep (using the mechanism selected by the PMCR[xIDEA] bits)
until the SYS_DEL timer expires. The PXA27x processor also has a configuration bit that allows
nVDD_FAULT to be ignored in sleep mode. Refer to Intel
Mechanical, and Thermal Specification and Intel
Mechanical, and Thermal Specification for SYS_DEL and PWR_DEL timing specifications.
®
Intel PXA27x Processor Family Design Guide
2
C Clock (PWR_SCL)
2
C clock output to the external PMIC. The I
2
C Data (PWR_SDA)
2
C data pin to the external PMIC. It functions like an
®
Clocks and Power Interface
®
PXA270 Processor Electrical,
PXA27x Processor Family Electrical,
2
C serial
II:3-3