External Clock Enable Configuration Scheme; Internal (To Pxa27X Processor) Clock Enable Configuration Design - Intel PXA27 Series Design Manual

8.3.3

External Clock Enable Configuration Scheme

The external clock enable configuration allows an external device to control when the SSP is
enabled. Configuring the SSP for external clock enable is performed by the use of the SSPCLKEN
signal. In this mode, the SSP must be the master of SSPSCLK and do not take an external or
network clock as the base clock.
See Figure 8-3
configuration.
Figure 8-3. External Clock Enable Configuration Scheme Block Diagram
8.3.4 Internal (to PXA27x Processor) Clock Enable Configuration
Design
The physical connections for the internal clock enable configuration design using internal clock
enable are identical to those for the standard SSP configuration design; although certain
configurations cause a different SSP within the processor to generate SSPSCLK regardless of
whether the master of the SSPSCLK has data to send. In this mode, the SSP, which is internally
being enabled, must be the master of SSPSCLK.
See Figure 8-4
design. In this example, SSP1 is the master of SSPSCLK and SSP2 is internally forcing SSP1 to
generate SSPSCLK using the internal signal tx_not_empty2. Doing so allows SSP2 of the PXA27x
processor to send data to Peripheral SSP #2. While Peripheral SSP #1 would also receive the
SSPSCLK, it would not receive a Frame signal (SSPSFRM) from SSP1 of the PXA27x processor,
and therefore, would not receive any data. In this example, the only function of SSP1 of the
PXA27x processor is to generate the SSPSCLK signal.
®
Intel PXA27x Processor Family Design Guide
for illustration of the physical connection of the external clock enable
®
Intel PXA27x Processor
SSP
for example of the physical connections in the internal clock enable configuration
SSPSCLK
SSPSFRM
SSPRXD
SSPTXD
SSPCLKEN
Clock Enable
from External
Source
SSP Port Interface
Peripheral SSP
II:8-5