Sram Signals; Sram Interface Signals - Intel PXA27 Series Design Manual

6.5.4.1

SRAM Signals

See Table 6-11
Table 6-11. SRAM Interface Signals
Signal Name
nCS<5:0>
MA<25:0>
MD<31:0>
DQM<3:0>
nWE
nOE
RDnWR
®
Intel PXA27x Processor Design Guide
for the list of signals required to interface to SRAM devices.
Direction Polarity

SRAM Interface Signals

Output Active Low
Output NA
Bidirectional NA
Output Active High
Output Active Low
Output Active Low
Miscellaneous I/O Signals
Output Active High
System Memory Interface
Description
Chip selects for static memory
Output address to all memory types
Do no use MA0 for byte addressing because all SRAM
devices must have a minimum bus width of 16 bits when
interfacing to the PXA27x processor memory controller. Use
MA0 to address the upper 64 Mbytes of memory within a 128
Mbytes partition.
Bidirectional data for all memory types
Data byte enable control
DQM<0> corresponds to MD<7:0>
DQM<1> corresponds to MD<15:8>
DQM<2> corresponds to MD<23:16>
DQM<3> corresponds to MD<31:24>
0 = Do not enable corresponding byte
1 = Enable corresponding byte
Write enable for SRAM memory
Output enable for static memory
Data direction signal to be used by output transceivers
0 = MD<31:0> is driven by the PXA27x processor
1 = MD<31:0> is not driven by the PXA27x processor
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