Layout Notes; Active Color, 18-Bit Per Pixel Mode; Active Color 16-Bit-Per-Pixel Display Typical Connection - Intel PXA27 Series Design Manual

LCD Interface
Figure 7-7. Active Color 16-bit-per-pixel Display Typical Connection
7.5.7.3

Layout Notes

Refer to Section 7.4, "Layout Notes,"
7.5.8

Active Color, 18-bit per pixel Mode

An active color display does not send dithered data to the panel. The lines driven represent the
digital value of the pixel being transmitted. A single pixel is transmitted per clock cycle. The bits of
data describe the intensity level of the red, green, and blue for each pixel.
Note: If the system design incorporates PCMCIA interface, LCD and MSL (Baseband Interface), refer to
Part II, Section 16.1, "Overview,"
simultaneously.
II:7-18
LDD<0>
LDD<1>
LDD<2>
LDD<3>
LDD<4> MSB of blue
LDD<5>
LDD<6>
LDD<7>
LDD<8>
LDD<9>
LDD<10> MSB of green
LDD<11>
LDD<12>
LDD<13>
LDD<14>
LDD<15> MSB of red
L_PCLK_WR
L_LCLK_A0
L_FCLK_RD
L_BIAS
for layout notes and considerations.
for important information on using these interfaces
®
Intel PXA27x Processor Family Design Guide
B0
B1
B2
B3
B4
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
CLOCK
HORIZ. SYNC
VERT. SYNC
DATA ENABLE