Usb On-The-Go Transceiver Usage - Intel PXA27 Series Design Manual

'USB Client Controller
USB On-The-GO
12.4.3
See Figure 12-4
(OTG) operation. Each of the configurations are described in detail.
Note: The PXA27x processor does not provide:
•
Direct connection to the USB Vbus
•
Control of the USB Vbus
Figure 12-4. USB OTG Configurations
U S B H o s t
P o rt 1
U S B C lie n t
U S B H o s t
P o r t 2
U S B H o s t
P o r t 3
The USB Host port 2 transceiver is designed in accordance with the Pull-up/Pull-down Resistors
Engineering Change Notice to the USB 2.0 Specification to provide on-chip resistors and OTG
compliant transceiver operation. The USB Host controller port 2 multiplexor is a bidirectional I/O
mux that connects to the USB Host port 2 transceiver and the single-ended I/O through the GPIO.
The port 2 multiplexor provides an interface that allows the USB device control (UDC) port or
USB host control (UHC) port 2 to connect to the UHC port 2 transceiver for direct bi-directional
connection to the USB. The port 2 multiplexor also provides an interface that allows the UDC port,
UHC port 2 and the UHC port 3 to connect to single-ended I/O through the GPIOs.
The PXA27x processor OTG transceiver consists of two pull-up resistors and one pull-down
resistor on each D+ and D-.
•
The resistors are enabled using the
pull-down enable bits (DPPUBE, DMPUBE, DPPUE, DMPUE, DPPDE, DMPDE). See
Figure 12-5
pull-down resistors.
•
As shown in
for USB host controller data.
•
As shown in
when host port 2 is being used for USB device controller data.
II:12-6
Transceiver Usage
for illustration of each of the configurations provided to support USB On-The-Go
P o r t 1
T ra n s c e iv e r
M U X
U P 2 O C R [H X S ]
U P 2 O C R [H X O E ]
M U X
U P 2 O C R [S E O S ]
P o rt 3
T ra n s c e iv e r
U P 3 O C R [C F G ]
for illustration of the on-chip Host port 2 transceiver pad with the pull-up and
Figure 12-5, SW3 is enabled for both D+ and D- when Host port 2 is being used
Figure 12-5, SW1 on the D+ pad is enabled and SW1 on the D- pad is disabled
D if f e re n t ia l P o r t
(U S B H _ P ,U S B H _ N )
D if f e re n t ia l P o r t
E n a b le
(U S B C _ P ,U S B C _ N )
S in g le -E n d e d
GPIO
S in g le -E n d e d
P o r t 3
"USB Port 2 Output Control Register (UP2OCR)"
®
Intel PXA27x Processor Family Design Guide
T o U S B
To U S B
GPIO
To U S B
P o rt 2
T o U S B
pull-up/