Schematics / Block Diagram; Lcd Interface Signal List - Intel PXA27 Series Design Manual

Note: The software must be enabled for an active 16-bit per pixel panel.
Table 7-8. LCD Interface Signal List
PXA27x
LCD Panel
Processor
Signal Name
Signal Name
LDD<15:12>,
R<3:0>,G<3:0>,
LDD<10:7>,
B<3:0>
LDD<4:1>
L_PCLK_WR CLOCK
HORIZONTAL
L_LCLK_A0
SYNC.
VERTICAL
L_FCLK_RD
SYNC.
L_BIAS DATA ENABLE
Note: Names used for "LCD Panel Pin" are representative names and do not match those on all LCD
panels. Similarly, not all signals are required for all modes of operation. Refer to the LCD panel
reference documentation for information on:
•
Specific signals required for correct LCD operation
•
Correct names of the signals used by the LCD panel manufacturer
7.5.6.2

Schematics / Block Diagram

See Figure 7-6
connections serve as a guide for designing systems that contain active LCD displays. The most
significant byte (MSB) of each color is indicated.
The sample below shows four red, four green, and four blue bits on the LCD panel. However,
different active display panels might have more or different data lines. Consult the LCD panel
manufacturer's documentation for the actual data lines.
®
Intel PXA27x Processor Family Design Guide
Type
Bidirectional Data lines used to transmit data values to the LCD display module.
Output Pixel clock used by the LCD display module to clock the pixel data into the panel.
Output Used by active (TFT) display module as the horizontal synchronization signal.
Output Used by active (TFT) display module as the vertical synchronization signal.
Used as the output-enable to signal when data is latched from the data pins using
Output
the pixel clock.
for illustration of typical connections for a 12 bpp active panel display. The sample
Description
LCD Interface
II:7-15