Overview; Signals - Intel PXA27 Series Design Manual

Inter-Integrated Circuit (I
9.1

Overview

The Inter-Integrated Circuit (I
(PXA27x processor) to serve as a master and slave device residing on the I
serial bus developed by the Philips Corporation consisting of a two-pin interface. SDA is the serial
data line and SCL is the serial clock line. A complete list of features and capabilities are found in
2
the I C Bus Specification.
Using the I
microcontrollers for system management functions. The serial bus requires a minimum of
hardware for an economical system to relay status and reliability information to an external device.
2
The I C bus interface unit is a peripheral device that resides on the PXA27x processor internal bus.
Data is transmitted to and received from the I
information is relayed through a set of memory-mapped registers. Refer to the I
Specification for complete details on I
9.2

Signals

See Table 9-1
2
Table 9-1. I C Signal Description
Signal Name
SDA
SCL
2
The I C bus serial operation uses an open-drain, wired-AND bus structure that allows multiple
devices to drive the bus lines and to communicate status on events such as arbitration, wait states,
and error conditions. For example, when a master drives the SCL during a data transfer, it transfers
a bit every time the clock is high. When the slave is unable to accept or drive data at the rate that
the master is requesting, the slave holds SCL low between the high states to insert a wait interval.
The master's clock is only altered by a slow slave peripheral keeping the clock line low or by
another master during arbitration.
2
The I C bus allows design of a multi-master system; meaning more than one device can initiate
data transfers at the same time. To support this feature, the I
AND connection of all I
provided they are driving identical data. The first master to drive SDA high while another master
drives SDA low loses the arbitration. The SCL consists of a synchronized combination of clocks
generated by the masters using the wired-AND connection to the SCL.
®
Intel PXA27x Processor Family Design Guide
2
C) bus interface unit allows Intel
2
C bus lets the PXA27x processor interface to other I
for the description of the I
Input/Output
Bidirectional Serial data
Bidirectional Serial clock
2
C interfaces to the I
2
C)
2
C bus using a buffered interface. Control and status
2
C bus operation.
2
C bus interface unit signals.
Description
2
C bus arbitration relies on the wired-
2
C bus. Two masters can drive the bus simultaneously,
®
PXA27x Processor Family
2 2
C bus. The I C bus is a
2
C peripherals and
2
C Bus
9
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