Internal SRAM
Figure 4-1. Internal SRAM Block Diagram
To Clocks/Power
Management Blcok
Control/Status
Registers
Power Management
4.4
Layout Notes
The power caps allows the internal SRAM to be powered up during sleep. Refer to
detailed information.
II:4-2
To System Bus
System Bus Interface
Bank Muxing and Control
Queue
Queue
Bank 0
Bank 1
Memory Array
§§
®
Intel
PXA27x Processor Family Design Guide
Queue
Queue
Bank 2
Bank 3
ISRAM_001_P2
Section 3.4
for