Intel PXA27 Series Design Manual page 182

Memory Stick Host Interface
Figure 17-1. Memory Stick Implementation Block Diagram
17.4 Layout Notes
The maximum switching frequency of the memory stick is 20 MHz. While it is important to use
good layout practices, it does allow for some flexibility in the design. Follow all general layout
practices. The Sony Memory Stick Standard, Format Specification Version 1.3 incorporates several
design concepts that make a memory stick application more robust, such as dual pins for both VSS
and VCC. Use of these concepts helps avoid any problems.
SCLK switches at a much higher frequency than any of the other signals. To help avoid spurious
transactions of the other signals, ensure SCLK is physically and electrically isolated from BS and
SDIO.
Each VSS and VCC pin from the socket must be separately routed to the appropriate power/ground
plane. Do not simply connect these pins at the socket.
The Sony Memory Stick Standard, Format Specification Version 1.3 requires that when a memory
stick is inserted VSS is the first pin to make contact. The specification also requires INS to be the
last pin to make contact upon insertion.
II:17-2
MSBS
MSSDIO
R
PU
nMSINS
MSSCLK
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Intel PXA27x Processor Family Design Guide
VSS
1
BS
2
VCC
3
SDIO
4
INS
6
SCLK
8
VCC
9
VSS
10