Alternate Bus Master Block Diagram; Alternate Bus Master Layout Notes; Alternate Bus Master Mode - Intel PXA27 Series Design Manual

System Memory Interface
6.5.7.2

Alternate Bus Master Block Diagram

See Figure 6-12
Figure 6-12. Alternate Bus Master Mode
6.5.7.3

Alternate Bus Master Layout Notes

Refer to Part II: Section 6.5.1.3, "SDRAM Layout Notes,"
size, and routing guidelines. Refer to Intel
Thermal Specification and Intel
Specification documents for AC timing information.
II:6-32
for illustration of the connections.
PXA27x
PXA27x
Memory
Controller
PXA27x
GPIO
Block
®
PXA27x Processor Family Electrical, Mechanical, and Thermal
EXTERNAL SYSTEM
SDCKE
SDCLK<1>
nSDCS(0)
nSDRAS
nSDCAS
nWE
MA<25:0>
DQM<3:0>
MD<31:0>
RDnWR
GPIO<13> (MBGNT)
GPIO<14> (MBREQ)
for recommendation on trace lengths,
®
PXA270 Processor Electrical, Mechanical, and
§§
®
Intel PXA27x Processor Design Guide
External
SDRAM
Bank 0
Companion
Chip