Flash Block Diagram; Flash Layout Note; Block Diagram Connecting Synchronous Flash To Ncs<1:0 - Intel PXA27 Series Design Manual

System Memory Interface
6.5.2.2

Flash Block Diagram

See Figure 6-6
PXA27x processor memory controller. This particular configuration shown in
partitions (chip select 0 and chip select 1). It is not required that both partitions be populated with
synchronous flash memory.
Figure 6-6. Block Diagram Connecting Synchronous Flash to nCS<1:0>
nCS<3:0>
nSDCAS, nWE
SDCLK<0>
MA<25:1>
nOE
MD<31:0>
PXA27x Memory
Controller
6.5.2.3

Flash Layout Note

Refer to Section 6.4
®
Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel
Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information.
II:6-16
for illustration of the connection between the synchronous flash memory and the
0
SDCAS
23:2
15:0
0
SDCAS
23:2
31:16
for recommendations on trace lengths, size, and routing guidelines. Refer to
4Mx16
Sync. Flash
nCS
nADV
nWE
CLK
A<21:0>
nOE
DQ<15:0>
4Mx16
Sync. Flash
nCS
nADV
nWE
CLK
A<21:0>
nOE
DQ<15:0>
®
Intel PXA27x Processor Design Guide
Figure 6-6 uses two
4Mx16
Sync. Flash
1
nCS
SDCAS
nADV
nWE
CLK
23:2
A<21:0>
nOE
15:0 DQ<15:0>
4Mx16
Sync. Flash
1
nCS
SDCAS
nADV
nWE
CLK
23:2 A<21:0>
nOE
31:16
DQ<15:0>
MEM_003_P2
®
PXA27x