Index; Bypass Register..............................................................................ii: - Intel PXA27 Series Design Manual

Index

A
AC '97
II:D-9, II:E-5
AC '97 II:13-1
Achieve Minimum Power
Usage During All Power Modes I:5-2
Usage During Deep Sleep I:5-2
Achieve Minimum Power Usage
During Idle/13M/Run/Turbo I:5-3
During Sleep I:5-3
During Standby I:5-3
Active Color
12-bit per pixel Mode II:7-16
16-bit per pixel Mode II:7-18
18-bit per pixel Mode II:7-20
Alternate Bus Master
Block Diagram II:6-33
Interface II:6-30
Layout Notes II:6-33
Signals II:6-32
Alternate Function During Standby and Sleep Mode II:18-4
B
Backlight Inverter II:7-4
Baseband Interface II:16-1
Baseband/Multimedia Interface
II:D-10
Block Diagram
II:3-4, II:4-1, II:5-2, II:5-4, II:5-5, II:6-5, II:8-3, II:11-2,
II:12-2, II:13-2, II:14-3, II:14-5, II:14-6, II:18-
3, II:18-7, II:18-9, II:18-11, II:19-4, II:21-2,
II:22-2, II:23-2, II:25-3, II:27-3
Block Diagram/Schematic II:24-3
Block Diagram for
USB Host Differential Connection (Port 1 or Port 2)
II:20-2
USB Host Single-Ended Connection (Port 3) II:20-4
Block Diagrams II:20-2
Block Diagrams for
USB Host Port 2 (Differential or Single-Ended) II:20-3
Bluetooth UART II:10-5
Block Diagram II:10-5
Signals II:10-5
Boundary-Scan Register II:26-8
Bus Host Controller, Universal Serial II:D-10
®
Intel PXA27x Processor Family Design Guide
Bus-Powered Device II:12-5
Bypass Register II:26-7
C
Capture-DR State II:26-11
Capture-IR State II:26-13
Cautions I:4-4
Channel Access/Control Block II:22-2
Channels 4 - 11 Blocks II:22-3
Clock and Power Manager
II:D-1, II:E-1
Clock Interface II:3-6
Clock Interface Signals II:3-1
Clock Manager
II:D-1
Clocks and Power Interface II:3-1
CODEC, BITCLK Signal II:14-6
Companion Components, PXA27x Processor II:E-1
Contrast Voltage II:7-3
Controller, USB II:D-10
Crystals/Oscillators
II:E-1
D
Data-Specific Registers II:26-9
Debug Registers II:26-16
Debug/Test
II:D-15
Design Check List I:3-1
Differences
PXA27x and PXA25x Processors II:D-1
Digital-to-Analog Converter II:9-2
DMA Controller
II:D-3, II:E-3
DMA Controller Interface II:5-1
Document Organization and Overview I:1-1
E
Example Power Supply Utilizing Minimal Regulators I:4-2
Exit1
DR State II:26-12
IR State II:26-13
Exit2
IX-1