Interface To External Charge Pump Device (Otg) - Intel PXA27 Series Design Manual

12.4.5

Interface to External Charge Pump Device (OTG)

In addition to interface options to internal and external OTG transceivers, the UDC provides
control outputs and interrupt inputs to drive and monitor an external charge pump device. In this
mode, D+ and D- signals of the USB are output using the on-chip OTG transceiver and the Vbus
interface provided by an external charge pump device. In this mode, the HXS bit in
Output Control Register (UP2OCR)"
•
UDC
•
D+, D-, and transmit enable signals of the USB host controller
These signals are output through the USB host controller port 2 transceiver.
In addition, to enable the driving of Vbus and the driving of pulses on Vbus, the
Output Control Register (UP2OCR)"
•
Charge pump Vbus enable (CPVEN) control output bit
•
Charge pump Vbus pulse enable (CPVPE) control output bit
.Additionally,
external charge pump device:
•
Vbus valid 4.0
•
Vbus valid 4.4
•
Session valid
•
Session request protocol (SRP) detected interrupt
®
Intel PXA27x Processor Family Design Guide
uses the control multiplexors to select between the following:
provides:
"USB Port 2 Output Control Register (UP2OCR)"
'USB Client Controller
"USB Port 2
"USB Port 2
provides inputs to interface to the
II:12-9