Signals - Intel PXA27 Series Design Manual

2
I S Interface
14.2

Signals

See Table 14-1
2
Table 14-1. I S Controller Interface to CODEC
Name
SYSCLK
BITCLK
SYNC
SDATA_OUT
SDATA_IN
II:14-2
for the list of signals between the I
Direction
System Clock = BITCLK x 4, used by the CODEC only. The I
SYSCLK generates a clock frequency between approximately 2 MHz
and 12.2 MHz by dividing down the PLL clock with a programmable
divisor. This frequency is always 256 times the audio sampling
Output
frequency. SYSCLK is driven out of the PXA27x processor I
controller only if BITCLK is configured as an output. If BITCLK is
supplied by the CODEC, the SYSCLK GPIO pin are used for an
alternate function.
BITCLK supplies the serial audio bit rate, which is the basis for the
external CODEC bit-sampling logic. BITCLK is one-quarter the
frequency of SYSCLK and is 64 times the audio sampling frequency.
One bit of the serial audio data sample is transmitted or received
Input or Output
each BITCLK period. A single serial audio sample comprises a "left"
and "right" signal, each containing either 8, 16, or 32 bits. BITCLK are
configured either as an input or as an output. If BITCLK is an output,
SYSCLK must be configured as an output.
SYNC is BITCLK divided by 64, resulting in an 8-KHz to 48-KHz
Output signal. The state of SYNC denotes whether the current serial data
samples are left or right channel data.
Output Serial audio output data to CODEC
Input Serial audio input data from CODEC
2
S and an external CODEC device.
Description
®
Intel PXA27x Processor Family Design Guide
2
S
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S