Block Diagram - Intel PXA27 Series Design Manual

6.3

Block Diagram

See the block diagram in
PXA27x processor are used to interface to flash, static memory, SDRAM, PC Card/Compact Flash,
and the use of an alternate bus master.
Figure 6-1. General Memory Interface Configuration
nSDCS<2>
nSDCS<3>
SDCLK<2>, SDCKE
nSDCS<1>
SDCKE
SDCLK<0>
nSDCS<0>
nOE
RDnWR
MBGNT
MBREQ
PXA27x
Processor
Memory
DQM<3:0>
Controller
nSDRAS, nSDCAS, nWE
Interface
nOE
MD<31:0>
MA<25:0>
Card Control
nCS<0>
nCS<1>
nCS<2>
SDCLK<0>
nCS<3>
nCS<4>
nCS<5>
RDY
NOTE:
Static Bank 0 must be populated by
"bootable" memory
®
Intel PXA27x Processor Design Guide
Figure 6-1 for illustration of how the memory controller signals of the
SDRAM Partition 3
(up to 256MB)
SDRAM Partition 2
(up to 256MB)
SDRAM Partition 1
(up to 256MB)
SDRAM Partition 0
(up to 256MB)
Alternate
Bus Master
Static Bank 0
(up to 128MB)
Static Bank 1
(up to 128MB)
Static Bank 2
(up to 64MB)
Static Bank 3
(up to 64MB)
Static Bank 4
(up to 64MB)
Static Bank 5
(up to 64MB)
System Memory Interface
SDRAM Memory Interface
Up to 4 partitions of SDRAM
memory (16- or 32-bit wide)
Buffers and
Transceivers
Static Memory or
Variable Latency I/O Interface
Up to 6 banks of ROM, Flash,
SRAM, Variable Latency I/O,
(16- or 32-bit wide)
NOTE:
Static Bank 0 must be populated by
"bootable" memory
PC Card Memory Interface
Up to 2-socket support.
Requires some
external buffering.
Synchronous Static
Memory Interface
Up to 4 banks of synchronous
Flash (nCS<3:0>).
(16- or 32-bit wide)
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