Block Diagram; Standard Ssp Configuration Scheme - Intel PXA27 Series Design Manual

Table 8-1. SSP Serial Port I/O Signals (Sheet 2 of 2)
Name
SSPSCLK2EN
SSPSCLK3
SSPSYSCLK3
SSPSFRM3
SSPTXD3
SSPRXD3
CLK_EXT
8.3

Block Diagram

8.3.1

Standard SSP Configuration Scheme

The Standard SSP configuration scheme is the most usual method of configuration and allows one
SSP to interface directly to another SSP on another device.
This configuration allows for a number of possible configurations. The SSPSCLK is either a
master or a slave to the peripheral. Likewise, the SSPSFRM is also programmed to be a master or a
slave to the peripheral. This allows for one physical connection to result in either of four
configurations with only software changes:
•
Master to SSPSCLK/master to SSPSFRM
•
Master to SSPSCLK/slave to SSPSFRM
•
Slave to SSPSCLK/master to SSPSFRM
•
Slave to SSPSCLK and slave to SSPSFRM
See Figure 8-1
®
Intel PXA27x Processor Family Design Guide
Direction
SSPSCLK2EN is an asynchronous external enable for
SSPSCLK2. This function is multiplexed with other alternate
functions. Refer to
Input
the Intel
SSPSCLK2EN is multiplexed with the SSPEXTCLK2 alternate
function (refer to
SSPSCLK3 is the serial bit clock used to control the timing of a
transfer. SSPSCLK3 is generated internally (master mode) or is
Inout
supplied externally (slave mode) as indicated by
SSPCR1_3[SCLKDIR].
SSPSYSCLK3 is four times the SSPSCLK3 value when using
Output Audio Clock PLL Select (SSACD_2[ACPS]) and Audio Clock
Divider (SSACD_2[ACDS]).
SSPSFRM3 is the serial frame indicator that indicates the
beginning and the end of a serialized data word. SSPSFRM3 is
Inout
generated internally (master mode) or is supplied externally (slave
mode) as indicated by SSPCR1_3[SFRMDIR].
Output SSPTXD3 is the transmit data (serial data out) serialized data line.
Input SSPRXD3 is the receive data (serial data in) serialized data line.
CLK_EXT is an external Network clock that replaces the internal
13 MHz clock. Use CLK_EXT when SSCR0_x[NSC] is set and
Input
SSCR1_x[SCLKDIR] is cleared. CLK_EXT is used by multiple
SSPs.
for illustration of the physical connections of the above configurations.
Description
Chapter 24, "General Purpose I/O Controller,"
®
PXA27x Processor Family Developers Manual .
Chapter 24, "General-Purpose I/O
SSP Port Interface
of
Controller").
II:8-3